Transistor

Details Transistor Transistor

2007-05-01

2007-05-01

Le, Thao X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular chip input/output means

C257S202000, C257S908000, C257SE27108

Reexamination Certificate

active

10967129

ABSTRACT:
A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode604sandwiched therebetween, one of the impurity regions has respective contact holes (a first contact hole601and a second contact hole602) and the other impurity region has a contact hole (a third contact hole603), and contacts of the contact holes601to603or regions605to607each including a margin for a contact are arranged so as to be a triangular lattice except for the gate electrode604.

REFERENCES:
patent: 5731613 (1998-03-01), Yamazaki et al.
patent: 6028580 (2000-02-01), Kosegawa et al.
patent: 6462723 (2002-10-01), Yamazaki et al.
patent: 7006177 (2006-02-01), Hirakata et al.
patent: 06-326214 (1994-11-01), None

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