Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation
Reexamination Certificate
2001-02-21
2003-02-04
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With pn junction isolation
C257S105000, C257S106000, C257S481000, C257S601000, C257S603000, C257S910000
Reexamination Certificate
active
06515345
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to electronics, in general, and to semiconductor components and methods of manufacturing.
Many electronic components, equipment, and high speed data and/or communication lines are highly sensitive to voltage spikes or surges caused by ElectroStatic Discharge (ESD), Electrical Fast Transients (EFT), and lightning. Accordingly, these highly sensitive components, equipment, and data lines must be protected from the voltage spikes or surges. Transient overvoltage protection or Transient Voltage Suppression (TFS) techniques are used to provide the necessary protection from the voltage spikes or surges. Many different TVS techniques exist including those techniques that use a single semiconductor die containing multiple devices and other techniques that use multiple semiconductor dice where each die contains a single device.
To minimize the effect of the parasitic bipolar and field effect transistors, the junction isolation can be formed by using isolation wells or tubs having heavy doping concentrations and deep junction depths reaching at least fifty micrometers into the semiconductor die. These isolation wells or tubs are formed during diffusion steps performed at very high temperatures and lasting for many hours. Furthermore, these isolation wells or tubs consume large amounts of area in the semiconductor die. Therefore, minimizing the problems associated with the parasitic bipolar and field effect transistors produces many other problems including a time-consuming manufacturing process and a large semiconductor die area required for the deep and heavily doped junction isolation.
An example of the TVS techniques using multiple semiconductor dice is a component commercially available from Semtech Corporation as part number LC03-6. In this component, four separate dice are wire bonded together in a single component package. Each semiconductor die has two back-to-back diode pairs, and each back-to-back diode pair comprises a low-voltage diode and a high-voltage diode to reduce the net capacitance of the back-to-back diode pair. This multiple die approach eliminates the parasitic bipolar and field effect transistor problems associated with junction isolation, but this multiple dice approach requires a more complicated, more time consuming, and more costly assembly process.
Accordingly, a need exists for a semiconductor component to protect electronic components, equipment, and data lines from voltage spikes or surges. It is desired for the semiconductor component to eliminate or at least E minimize the problems associated with junction isolation. A need also exists for a simple and cost-effective method of manufacturing the semiconductor component.
REFERENCES:
patent: 5536958 (1996-07-01), Shen et al.
patent: 5716880 (1998-02-01), Verma
patent: 5821586 (1998-10-01), Yamaguchi et al.
patent: 6075276 (2000-06-01), Kitamura
patent: 6348716 (2002-02-01), Yun
Pearse Jeffrey
Robb Francine Y.
Eckert George
Semiconductor Components Industries LLC
Warren Matthew E.
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