Transient signal suppression circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

Patent

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Details

307247A, 307480, 307234, 307542, H03K 1756, H03K 1900

Patent

active

045256357

ABSTRACT:
An input signal is applied to a first flip-flop whose output is coupled to the input of a second flip-flop. The two flip-flops are clocked, at a time t.sub.1 and at a subsequent time t.sub.2, for storing the value (SI.sub.1) of the input signal at time t.sub.1 in one flip-flop and for storing the value (SI.sub.2) of the input signal at time t.sub.2, in the other flip-flop. Logic gates coupled between the first and second flip-flops and a third, set/reset, flip-flop sense the values (SI.sub.1 and SI.sub.2) of the input signal stored by the first and second flip-flops and either: (a) set the third flip-flop to a condition indicative of the value of the input signal at times t.sub.1 and t.sub.2 if SI.sub.1 is equal to SI.sub.2 ; or (b) maintain the third flip-flop undisturbed in the state to which it was set just prior to t.sub.1 if SI.sub.1 is not equal to SI.sub.2.

REFERENCES:
patent: 3611158 (1972-10-01), Strathman
patent: 3725792 (1973-04-01), Kellogg
patent: 3828258 (1974-08-01), Hills et al.
patent: 3835336 (1974-09-01), Block
patent: 3950705 (1976-04-01), Fuerherm
patent: 3989960 (1976-11-01), Kodama
patent: 4057738 (1977-11-01), Nishimura
patent: 4282488 (1981-08-01), Norman et al.

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