Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Signal transmission integrity or spurious noise override
Reexamination Certificate
2000-01-27
2001-12-11
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Signal transmission integrity or spurious noise override
C327S310000, C327S389000
Reexamination Certificate
active
06329866
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a transient current producing method, transient current producing circuit, related semiconductor integrated circuit and logical circuit in a high-speed operation logical circuit and more particularly to the transient current producing method, transient current producing circuit, related semiconductor integrated circuit and logical circuit to implement high-speed switching operations and low power consumption.
2. Description of the Related Art
In a high speed logical circuit, to ensure its high speed operation, in the case of large load capacity in particular, a method is utilized in which its loaded capacity is charged and discharged at high speed by producing a transient current.
FIG. 7
is an example of a conventional logical circuit containing a transient current producing circuit (which is also called an “active pull-down or active pull-up circuit” in some cases).
As shown in
FIG. 7
, a drain of a p-channel MOS transistor
1
(hereinafter referred to as a “PMOS transistor”) is connected to a drain of an n-channel MOS transistor
2
(hereinafter referred to as an “NMOS transistor”), to a gate of the NMOS transistor
3
, to a base of an NPN-type bipolar transistor
6
(hereinafter referred to as an “NPN transistor”) through a resistor
4
and to a collector of the NPN transistor
6
through a resistor
5
, and a source of the PMOS transistor
1
is connected to a terminal of a power supply VDD, sources of the NMOS transistors
2
and
3
and an emitter of the NPN transistor
6
are connected to the ground, a capacitor device
7
is connected between the base of the NPN transistor
6
and the ground, gates of both the PMOS transistor
1
and the NMOS transistor
2
are connected to an input IN, a drain of an NMOS transistor
3
is connected to an output OUT.
A first CMOS circuit
8
is composed of the PMOS transistor
1
and the NMOS transistor
2
. A second CMOS circuit is composed of the NMOS transistor
3
. A transient current producing circuit
10
is comprised of the resistors
4
and
5
, the NPN transistor
6
. Also, the output OUT is connected through a terminating resistor RTT to a terminal of a terminating voltage VTT. The logical circuits shown as examples are generally called an output circuit which is used to output a logical signal through a transmission line such as a bus line connected among two or more integrated circuits.
FIG. 8
is the timing chart showing operations of logical circuits containing the transient current producing circuit
10
shown in FIG.
7
. In
FIG. 8
, during a section A where the input IN is at the same potential as the terminal of the power supply VDD and at a high level, an output (node A) of the CMOS circuit
8
is at the same potential as the ground and at a low level and the NPN transistor
6
is in an OFF state.
Since the NMOS transistor
3
remains in its OFF state, the output OUT is at the same potential as the terminating power supply VTT and at a high level. After that, if a level of the input IN becomes low, though the PMOS transistor
1
is changed to be in its ON state during a section B, causing currents to be supplied to the resistor
4
, and the base of the NPN transistor
6
is delayed, by time constant of the resistors
4
and capacitor device
7
(the time period “t
1
” in FIG.
8
), in being turned ON.
The current of the PMOS transistor
1
during a period existing before the NPN transistor
6
is turned ON is only a current supplied to the gate of the NMOS transistor
3
by the NMOS transistor
3
and, therefore, a transition of the NMOS transistor from its OFF state to its ON state is speeded up.
A time “t
1
” after, the NPN transistor
6
is turned ON and a potential of the node A is clamped to a predetermined value. At this point, a steady state current flows from the terminal of the power supply VDD through the PMOS transistor
1
, a resistor
5
and the NPN transistor
6
towards the ground. In this state, since the NMOS transistor
3
is in its ON state, a current flows from the terminal of the terminating power supply VTT through a terminating resistor RTT to the NMOS transistor
3
. As a result, the potential of the output OUT drops by the current flowing from the terminal of the terminating power supply VTT to the terminating resistor, which is at a low level. After that, when the input IN again changes to a high level, though the PMOS transistor
1
changes to its OFF state during a section C and the NMOS transistor
2
changes to its ON state, since the NPN transistor is turned ON, the level of the node A rapidly becomes low. Accordingly, the NMOS transistor
3
changes to be in its OFF state.
In such logical circuits for producing logic signals described above, a reaction current always occurs and therefore the transient producing circuit serving as a discharging circuit to discharge such reaction currents is required. However, in the circuit having such a transient producing circuit, a current flows constantly during a rising period due to its time constant, causing a delay in switching among circuits. During the section B in
FIG. 8
, the NPN transistor
6
in the transient current producing circuit always remains ON, causing a steady state current to continue flowing, thus resulting in an increase in power consumption. Because of this increase in the power consumption, it is difficult to use the high-speed logical circuit described above in such applications as battery driving and the like where low power consumption is necessarily required. Accordingly, the logical circuit capable of preventing the flow of the steady state current, consuming little power and switching at high speed is strongly needed.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a transient current producing method, a transient producing circuit, a related semiconductor integrated circuit and logical circuit, which are capable of preventing a flow of a steady state current, consuming little power and switching at high speed.
According to a first aspect of the present invention, there is provided a method for producing a transient current including a step of amplifying the transient current occurring at a time of switching of a CMOS circuit wherein the amplification of the transient current prevents a flow of a steady state current in the circuit.
According to a second aspect of the present invention, there is provided a method for producing a transient current including steps of converting the transient current occurring at the time of switching of a CMOS circuit to a transient voltage, and converting the transient voltage to a transient current having a predetermined value and amplifying the transient current, wherein the amplification of the transient current serves to allow construction of a simple circuit.
In the foregoing, a preferable mode is one wherein the transient current is a feedthrough current flowing from a power supply to a ground at the time of switching of the CMOS circuit.
Also, a preferable mode is one wherein the transient current is a transient current flowing from the power supply to an output terminal of the CMOS circuit at the time of switching of the CMOS circuit or a transient current flowing from the output terminal to the ground.
According to a third aspect of the present invention, there is provided transient current producing means including:
a CMOS circuit;
a transient voltage converting means for converting the transient current occurring at the time of switching of the CMOS circuit to the transient voltage; and
the transient current producing means for converting the transient voltage to the transient current having a predetermined value and for amplifying the current, wherein the amplification of the transient current prevents a flow of a steady state current.
In the foregoing, a preferable mode is one wherein the transient voltage producing means is connected between the CMOS circuit and the power supply.
Also, a preferable mode is one wherein the transient
McGuireWoods LLP
NEC Corporation
Nguyen Hiep
Wells Kenneth B.
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