Patent
1996-12-13
1999-02-02
Barry, Esq., Lance Leonard
39520075, 395876, G06F 15164
Patent
active
058676643
ABSTRACT:
In a parallel processor system, a plurality of nodes each comprising a processor and a main storage unit are interconnected through a network, wherein a user process is executed under the control of an operating system in each of the nodes and inter-process communications are performed through the network for transmitting and receiving messages among the nodes. Reception buffers are provided in a main storage unit and addressed by pool pages, which are discontinuous in a logical address domain or in a real address domain, in a virtual space used by the user process executed by each node. Additionally, reception buffer control information is located on the main storage unit for managing the reception buffers. A node, when receiving a message, uses communication information included in the received message and reception buffer control information to calculate a real address in the reception buffers for storing the received message.
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patent: 5629928 (1997-05-01), Calvignac et al.
patent: 5634127 (1997-05-01), Cloud et al.
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Hamilton Patrick
Kosugi Hidenori
Barry, Esq. Lance Leonard
Hitachi , Ltd.
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