Transferring data between different clock domains

Details Transferring data between different clock domains Transferring data between different clock domains

2002-03-06

2004-04-20

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S239000

Reexamination Certificate

active

06724683

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to transferring data between different clock domains.
A transfer between different clock domains can be accomplished via a data synchronizer
110
(FIG.
1
). Data sending circuit
120
sends data to data receiving circuit
130
through the synchronizer. Data sending circuit
120
is clocked by a clock SCLK. Data receiving circuit
130
is clocked by a different clock RCLK. Synchronizer
110
has a data FIFO
140
, a FIFO full logic
150
, and a FIFO empty logic
160
. When sender
120
has data available for transfer, and the FIFO
140
is not full, the sender stores data in FIFO
140
(by asserting the WR signal). The sender must monitor the FIFO full logic
150
(the signal FULL) to prevent FIFO overrun.
When FIFO
140
is not empty, and receiver
130
is ready, the receiver reads data from the FIFO (by asserting the RD signal). The receiver
130
must monitor the FIFO empty logic
160
(the signal EMPTY) to prevent FIFO underrun.
The interaction between the FIFO full logic, the FIFO empty logic, the sender
120
, and the receiver
130
is complex, because actions that change the status of FIFO
140
can occur in either clock domain, and the results of these actions must be communicated to the other clock domain. The signals generated in one clock domain may have to meet the setup and hold time requirements for the other domain. For example, the input of data FIFO
140
is generated synchronously with sender's clock SCLK but the FIFO must meet the setup and hold time requirements with respect to receiver's clock RCLK. This adds a delay and reduces the throughput through the synchronizer.
SUMMARY
The invention is defined by the appended claims which are incorporated into this section by reference. Some features of the invention are summarized immediately below.
In one embodiment, meeting the setup and hold time requirements for the data is made easier because the data are made available to RCLK domain circuitry for more than one cycle of the sender's clock SCLK. Yet the synchronizer throughput is one data item per SCLK clock cycle. The synchronizer has a circular FIFO. Each entry in the FIFO has an output connected to the RCLK domain circuitry. The output of each entry is available to the RCLK domain for more than one SCLK clock cycle. Therefore, it is easier to meet the RCLK domain setup and hold time requirements.
A FIFO full logic and a FIFO empty logic are omitted. The sender writes a data item and a data valid flag to the synchronizer FIFO in each SCLK clock cycle. The receiver reads the FIFO in each RCLK clock cycle. The SCLK and RCLK clocks have the same frequencies. Synchronization between the SCLK domain and the RCLK domain is established at reset to ensure that the RCLK domain circuitry does not read any given FIFO entry too early or too late. After the reset, no signals are transferred from the RCLK domain to the SCLK domain.
In some embodiments, the SCLK and RCLK clocks have different frequencies.
In some embodiments, a synchronizer transfers data from a sender to a receiver which are clocked by the same clock signal but the clock signal has to propagate over unequal distances which results in a clock skew.
The invention is not limited to the embodiments described above. For example, the invention is not limited to embodiments without a FIFO full or FIFO empty logic, or to embodiments in which the synchronization between the RCLK and SCLK domains is established at reset, or other features described above. The invention is defined by the appended claims.


REFERENCES:
patent: 4674032 (1987-06-01), Michaelson
patent: 5768624 (1998-06-01), Ghosh
patent: 6338127 (2002-01-01), Manning

Affiliated with

Also associated with

Rating

Transferring data between different clock domains does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Transferring data between different clock domains, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transferring data between different clock domains will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3210760