Transfer controller with hub and ports architecture

Details Transfer controller with hub and ports architecture Transfer controller with hub and ports architecture

2000-04-06

2002-12-17

Patel, Ramesh (Department: 2121)

Data processing: generic control systems or specific application

Generic control system, apparatus or process

Sequential or selective

C700S002000, C700S005000, C700S007000, C700S019000, C700S011000, C700S012000, C710S002000, C710S022000, C710S023000, C710S026000, C710S028000, C710S107000, C712S034000, C712S036000, C712S038000

Reexamination Certificate

active

06496740

ABSTRACT:

This application claims priority under 35 USC §119 of British Application Number 99 09196.9, filed Apr. 21, 1999, in the United Kingdom Patent Office.
BACKGROUND OF THE INVENTION
1. Field of the Invention
General purpose multiprocessors, with a few exceptions, generally fall in a class of architectures which have been classified as ‘multiple instruction stream, multiple data stream processors’, sometimes labeled MIMD multiprocessors. This classification can be further divided into two sub-classes. These are:
(1) centralized shared memory architectures illustrated in FIG.
1
and
(2) distributed memory architectures illustrated in FIG.
2
.
In
FIG. 1
, the shared main memory functional block
100
may be accessed by any one of the four processors
101
,
102
,
103
,
104
shown. The external memory interface block
105
includes several possible sub-blocks among which are DRAM controller, SRAM controller, SDRAM controller, external disc memory interface, external ROM interface, RAMBus, or synchronous link DRAM interface and all other external memory devices.
The XDMA (external direct memory access) interface
106
is the interface to fully autonomous external devices. The external I/O interface
107
includes all other external interface: fast serial I/O port controller, parallel I/O interface, PCI bus controller, and DMA (direct memory access interface) controller are examples.
In
FIG. 2
in distributed memory multi-processor machine, the main memory is distributed among processor nodes
201
,
202
,
203
,
204
,
205
,
206
, and
207
as shown and all external memory interfaces are accomplished through the interconnection network
210
. External direct memory access is centralized at the XDMA port
208
which includes the XDMA control and I/O interface functions. Direct memory access (DMA) is distributed at each processor I/O Node or could be centralized as shown in the DMA functional block
209
.
Interchange of data in
FIG. 2
, from one processor node to another and from any processor node to external devices and memory is exceedingly complex and collisions caused by conflicting data transfer requests are frequent.
Systems having perhaps two to four processors might be of either the centralized shared memory type or the distributed memory type, but as the required processor count increases, the advantages of a distributed memory architecture become prominent. This is because a centralized shared memory
100
cannot support the bandwidth requirements of the larger number of processors.
The complexity of the interconnection network required in a distributed memory multiprocessor is one of elements of the cost of surmounting the bandwidth limitations of the shared memory system. Other elements of cost are addressing complexity and additional coherency and protocol requirements. The disadvantage of a distributed memory system is that this complex interconnection network has a formidable task, the communication of data between each and any pair of processors, which results in higher latency than the single, shared memory processor architecture.
Conventional digital signal processors (DSP) having a single processor typically include direct memory access, a method of memory access not requiring CPU activity, and conventionally this is accomplished by a ‘DMA’ functional block, which includes an I/O device and a controller function. This functional feature allows interface of external devices with CPU, internal memory, external memory, and other portions of the chip.
Direct memory access is usually the term used for external device interface, but external DRAM memory could be considered as simply another external device which has more demanding throughput requirements and would operate at a somewhat higher frequency than the typical frequency of a simple I/O device. The DMA interface is the communication link which relieves the central processing unit (CPU) from servicing these external devices on its own, preventing with loss of many CPU cycles which would be consumed in a direct CPU-external device interface.
Digital signal processing (DSP) differs significantly from general purpose (GP) processing performed by micro-controllers and microprocessors. One key difference is the typical strict requirement for real time data processing. For example, in a modem application, it is absolutely required that every sample be processed. Even losing a single data point might cause a DSP application to fail. While processing data samples may still take on the model of tasking and block processing common to general purpose processing, the actual data movement within a DSP system must adhere to the strict real-time requirements of the system.
As a consequence, DSP systems are highly reliant on an integrated and efficient DMA (direct memory access) engine. The DMA controller is responsible for processing transfer requests from peripherals and the DSP itself in real time. All data movement by the DMA must be capable of occurring without central processing unit (CPU) intervention in order to meet the real time requirements of the system. That is, because the CPU may operate in a software tasking model where scheduling of a task is not as tightly controlled as the data streams that the tasks operate on, the DMA engine must sustain the burden of meeting all real time data stream requirements in the system.
There are several approaches that may be taken to meet these requirements. The following is a brief summary of the conventional implementations of DMA engines, and their evolution into the unique I/O solution provided by the present invention, the transfer controller with hub and ports (TCHP) architecture.
2. Description of the Related Art
The conventional DMA engine consists of a simple set of address generators which can perform reads and writes of some, or perhaps all, addresses within a DSP system. The address generation logic is normally implemented as a simple counter mechanism, with a reload capability from a set of DSP memory-mapped registers. A typical use of a DMA controller is for the DSP to load the counters with a starting address and a count, representing the amount of data to transfer. The DSP must supply both the source and destination addresses for the transfer. Once this information has been loaded into the counters, the DSP can start the DMA via a memory mapped register write. The DMA engine then begins performing read and write accesses to move the requested data without further DSP intervention. The DSP is free to begin performing other tasks.
As the DMA performs read and writes to the source and destination locations, the addresses are incremented in each counter while the count is decremented. Once the count reaches zero, the transfer is complete and the DMA terminates. Most DMAs include a mechanism of signaling this ‘done’ state back to the CPU via a status bit or interrupt. In general the interrupt method is preferred because it does not require a polling loop on the DSP to determine the completion status.
The simplest DMAs provide for basic single dimensional linear transfers. More advanced DMA engines may provide multi-dimensionality, indexed addressing, and reverse and fixed addressing modes.
As DSP cores have reached higher and higher performance, applications have opened up which can utilize the increased processing capability. Along with this however, has come the need for higher speed, and higher complexity DMA engines. For example, if a previous generation DSP only had enough processing power for a single audio channel, a single DMA engine might be sufficient. However, when a new DSP architecture is introduced with ten times this performance, now multiple channels of audio could be processed. However, the DSP processing alone is not sufficient to provide the additional channel capacity. The DMA must also be enhanced to provide the data movement functions required for the multiple channels.
There are several features which are becoming increasingly common to DMAs which have attempted to address the issue of providing higher performance. The first is the inclusio

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