Patent
1993-02-01
1996-01-16
Envall, Jr., Roy N.
39520001, H01J 100
Patent
active
054855829
ABSTRACT:
At data transfer, a processor sends an address to an address bus and sends a data to a data bus. In a transfer control unit, a comparator compares an outside address signal inputted via the address bus with an inside address signal generated in an address generating part. When the signals coincide with each other, the comparator outputs a coincidence signal. Receiving the coincidence signal, a control part sends a write signal to a buffer and a data on the data bus is stored in the buffer. The address generating part proceeds to a next address according to the write signal. The data in the buffer is sent outside from a port thereafter. Thus, a program for high-speed data transfer is easily programmed with an ordinary code of a processor for general purpose.
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Okabayashi et al., "Network Structure and VLSI Implementation for a Parallel Computer: Adena", Integrated Circuits and Devices, ICD 89-152, pp. 1-8.
Envall Jr. Roy N.
Lintsai Paulina
Matsushita Electric - Industrial Co., Ltd.
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