Amplifiers – With semiconductor amplifying device – Including frequency-responsive means in the signal...
Reexamination Certificate
2003-02-27
2004-10-19
Nguyen, Patricia (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including frequency-responsive means in the signal...
C330S260000
Reexamination Certificate
active
06806776
ABSTRACT:
BACKGROUND
This Application claims priority from Korean Patent Application No. 2002-12223, the contents of which are incorporated herein by reference.
1. Field of the Invention
This disclosure teaches techniques related to transconductor tuning circuits. Specifically, techniques related to transconductor tuning circuits capable of controlling transconductance value in high speed while reducing effects from external environment are taught.
2. Background of the Related Art
Transconductors are generally used as basic elements of an IC(Integrated Circuit). However, transconductance values of such transconductors change because of the influence of manufacturing processes, surrounding temperature, and voltage of power supply, etc. Therefore, a tuning circuit is required for controlling the circuit to maintain a constant transconductance. This is specifically critical for circuits that require precise transconductance.
A conventional transconductor tuning circuit using a BiCMOS element is disclosed in “A 20-MHz sixth-order BiCMOS parasitic insensitive continuous-time filter and second-order equalizer optimized for disc-drive read channels”, IEEE J, Solid-State Circuits, Vol. 28, pp. 462-470, April, 1993. The BiCMOS transconductor tuning circuit disclosed in the above paper, is illustrated in FIG.
1
.
Referring to
FIG. 1
, a sub-circuit including reference numerals Q
6
,Q
9
,M
7
,M
10
is a basic circuit for a transconductor. Transconductance value of such a transconductor is controlled by an output voltage Vo of an error amplifier A
3
. The transconductor basic circuit is biased by MOS(Metal-Oxide Semiconductor) transistors M
5
and M
8
under control of a common-mode feedback(CMFB) amplifier. The transconductance control voltage Vo corresponding to a current difference k
T
&Dgr;i/2 is output through an error amplifier A
3
.
The differential input voltage is a voltage difference between voltages respectively applied to MOS transistors M
7
and M
10
. Assuming that the differential input voltage is &Dgr;V and that a current control ratio is k
T
, then a control value for an external transconductance(Gm) by an output voltage of the tuning circuit could be defined by the following formula.
G
m
=
k
T
Δ
i
/
2
Δ
v
/
2
=
k
T
R
ext
[
Formula
1
]
In the circuit of
FIG. 1
, a variable range of the current &Dgr;I flowing through a current source
1
is restricted within a narrow range by restricting the input voltage range(common mode range: CMR) of the error amplifier A
1
. Also, a CMFB circuit is used for compensating for an input voltage range of the error amplifier A
3
. Clearly, such a circuit is complex making it difficult to construct.
In order for a tuning circuit to stably control a voltage of a transconductor in high speed, the frequency range of operation of the tuning circuit should be maintained accordingly. A voltage difference, corresponding to a current difference k
T
&Dgr;i/2, passes through the multi-stage amplifier. Such a multi-stage amplifier consists of the error amplifier A
3
, transistors Q
6
and M
5
, or another transistors Q
9
and M
8
. Therefore, it is difficult to extend and compensate for a frequency range for stable operation of this closed loop.
The disclosed techniques are aimed at overcoming some of the disadvantages noted above. Specifically this disclosure is aimed at providing a transconductor tuning circuit capable of extending an operation frequency range while reducing effects from external environment.
SUMMARY
To overcome some of the disadvantages discussed above, there is provided a transconductor tuning circuit for controlling transconductance of a transconductor. The tuning circuit comprises a first MOS (Metal-Oxide Semiconductor) transistor. A source terminal of the first MOS transistor is connected to a power source. A gate terminal and a drain terminal of the first MOS transistor being connected to each other. A gate terminal and a drain terminal of a second MOS transistor being connected a first input terminal of a first error amplifier is connected to the gate terminal of the first MOS transistor. A second input terminal of the first error amplifier is connected to the gate terminal of the second MOS transistor. The first error amplifier outputs an output signal in form of a bias signal for controlling tuning of the transconductor.
In another specific enhancement, the transconductor comprises a first bipolar transistor connected for receiving the bias signal through a base of the first bipolar transistor, a collector terminal of the first bipolar transistor being connected to drain terminal of the first MOS transistor. A second bipolar transistor is connected for receiving the bias signal through a base of the second bipolar transistor, a collector terminal of the second bipolar transistor being connected to drain terminal of the second MOS transistor. A third MOS transistor is connected for receiving differential input signal generated from a differential input signal generating unit, a drain terminal of the third MOS transistor being connected to an emitter terminal of the first bioplar transistor. A fourth MOS transistor is connected for receiving differential input signal generated from the differential input signal generating unit, a drain terminal of the fourth MOS transistor being connected to an emitter terminal of the second bioplar transistor.
More specifically the differential input signal generating unit comprises a second error amplifier, a reference voltage being provided to a first input terminal of the second error amplifier, a first and a second voltage distribution resistance connected in series with a second input terminal of the second error amplifier. A fifth MOS transistor is provided, a source terminal of the fifth MOS transistor being connected to the power supply, a gate terminal of the fifth MOS transistor being connected to an output terminal of the second error amplifier. A feedback resistance element is connected between a drain terminal of the fifth MOS transistor and a second input terminal of the second error amplifier. A gate terminal of the third MOS transistor is connected to a drain terminal of the fifth MOS transistor, and a gate terminal of the fourth MOS transistor is connected to a node between the first and the second voltage distribution resistance.
Even more specifically a capacitor is connected between the output terminal of the second error amplifier and the drain terminal of the fifth MOS transistor.
Even more specifically a current source generating unit is connected to a drain terminal of the second MOS transistor, the current source generating unit being capable of generating a current source having a predetermined current ratio in response to an external control current generated from a transconductor controlling signal input unit.
Even more specifically, the current source generating unit comprises a cascade current mirror circuit connected for generating a current ratio of n:1.
Even more specifically, the transconductor controlling signal input unit comprises a sixth MOS transistor, a drain terminal of the sixth MOS transistor being connected to an external resistance, a source terminal of the sixth MOS transistor being connected to the power supply. A third error amplifier is provided for receiving a voltage drop signal of the external resistance through a non-inverted terminal of the third error amplifier, an external input signal being received through an inverted terminal of the third error amplifier, an output terminal of the third error amplifier being connected to a gate terminal of the sixth MOS transistor. A seventh MOS transistor is provided, a source terminal of the seventh MOS transistor being connected to the power supply, a drain terminal of the seventh MOS transistor being connected to the current source generating unit and a gate terminal of the seventh MOS transistor being connected to the output terminal of the third error amplifier.
Even more specifically, a capacitor for com
Cho Gea-ok
Lee Jeong-won
Lee Jung-eun
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