Amplifiers – With periodic switching input-output
Reexamination Certificate
2002-09-20
2004-12-14
Nguyen, Khanh Van (Department: 2817)
Amplifiers
With periodic switching input-output
C330S051000, C327S124000
Reexamination Certificate
active
06831507
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to transconductance amplifiers, that is amplifiers which produce an output current in response to an input voltage, and to analogue-to-digital converters (ADCs) employing such amplifiers. More particularly the invention relates to transconductance amplifiers in which an output current depends upon the difference between two input voltages, and to their applications.
BACKGROUND TO THE INVENTION
In many ADC designs an analogue input voltage is compared to a reference voltage (or a plurality of reference voltages) to produce a voltage output which can be used to generate a digital output code. Exemplary voltage comparators are described in U.S. Pat. No. 6,150,851, U.S. Pat. No. 6,356,148, U.S. Pat. No. 6,249,181 and D. R. Beck and D. J. Allstot, “An 8-bit, 1.8V, High Speed Analogue-to-Digital Converter” (http://students.washington.edu/beckdo/papers/techcon2000.doc) and P. Setty, J. Barner, J. Plany, H. Burger and J. Sonntag, “A 5.75b 350MSamples/S or 6.75b 150MSamples/S reconfigurable/ADC for a PRML Read Channel”, Session 9 IEEE International Solid-State Circuit Conference 5-7 February 1998 (ISSCC98). Sample and Hold (S/H) circuits for ADCs are also known, such as those described in U.S. Pat. No. 6,169,427 and U.S. Pat. No. 5,963,156 and N. Waltari and K. Halonen, “1.0-Volt, 9-bit Pipeline CMOS ADC”, 26
th
European Solid-State Circuit Conference Stockholm, Sweden 19-21 September 2002 which all use a conventional (voltage output) operational amplifier with switched capacitor feedback. Also known are Successive-Approximation-Register (SAR) analogue-to-digital converters (see, for example, J. L. McCreary and P. Gray, IEEE JSSC SC-10 pp371-9, Dec 1975) which compare an analogue input with the output of a digital-to-analogue converter (DAC), which DAC may employ a binary-weighted capacitor array to generate an analogue output voltage using charge redistribution between the capacitors.
The above-mentioned analogue-to-digital converters use voltage comparisons to generate a digital output. It will be appreciated that when comparing an input voltage to a reference voltage only gain, and not linearity is important since it is merely necessary to know whether the input is above or below the reference. However it is also known to simplify ADC circuits by summing currents generated by interpolating between reference voltages, and for this interpolation-type summing linearity is an important requirement. Interpolating ADCs are often used for low-resolution high-or medium-speed applications.
FIG. 1
shows a generalised circuit diagram of an exemplary stage of a current-mode interpolating ADC. Examples of ADCs with current-mode interpolation are described in M. P. Flynn and D. J. Alstot, “CMOS Folding A/D Converters with Current-Mode Interpolation”, IEEE JSSC, vol. 31, September 1996 pages 1248-1257; M. P. Flynn and B. Sheahan, “A 400MSample/S, 6-b CMOS Folding and Interpolating ADC” IEEE JSSC, vol. 33, Dec. 1998, pages 1932-1938; B-S Song, P. L. Rakers and S. F. Gillig, “A 1V, 6-b 50MSamples/S Current Interpolating CMOS ADC”, IEEE J. Solid-State Circuits, vol. 35, April 2000, pages 647-651.
Referring to
FIG. 1
a
, the general principle is to generate a plurality of comparison levels (five in
FIG. 1
) from a smaller set of reference voltages (two, VrefA and VrefB, in
FIG. 1
) by interpolating between the outputs from a set of amplifiers (two in FIG.
1
), each of which outputs represents the difference between an input signal and one of the references.
In the interpolating stage
100
of
FIG. 1
a
an input voltage on line
102
is provided to one input of first
104
and second
106
differential transconductance amplifiers. A second input to the first transconductance amplifier
104
is provided by a first reference voltage VrefA on line
108
and a second input to differential transconductance amplifier
106
is provided by a second reference voltage VrefB on line
110
. Each differential transconductance amplifier generates an output current in proportion to the difference between the voltages on its two inputs, the ratio of output current to input voltage difference being termed the transconductance. Amplifiers
104
and
106
are drawn as current sinks but preferably their output currents can be of either positive or negative polarity according to the polarity of Vin-VrefA and Vin-VrefB respectively.
FIG. 1
b
illustrates one possible implementation of a transconductance amplifier
130
suitable for use for transconductance amplifiers
104
and
106
. The transconductance amplifier comprises a pair of input transistors
132
,
134
with inputs from, respectively, Vin
102
and one of VrefA
108
and VrefB
110
, and a common source connection connected to a constant current sink
136
. The drain connections of transistors
132
and
134
are connected to respective input and output connections of a current mirror enclosed by dashed line
138
, and a current output connection
140
is taken from the junction of the drain of transistor
134
with the output of current mirror
138
. Each of transistors
132
,
134
passes an incremental current given by its transconductance gm, multiplied by the incremental gate input voltage of the transistor so that the output current is given by Iout=Gm.(Vin−Vref) where the transconductance, Gm, of the amplifier is equal to gm.
The output current from transconductance amplifier
104
is input to or drives a first current mirror
112
and the output current from transconductance amplifier
106
drives a second current mirror
114
. Current mirror
112
comprises a plurality of constant current generators
112
a-e
. In a conventional manner, a voltage on line
116
sets the current through element
112
a
to be the same as the output current flowing into differential transconductance amplifier
104
. This same drive voltage is also provided to elements
112
b-e
to provide constant current outputs on lines
118
a-d
determined by the output current of transconductance amplifier
104
.
FIG. 1
c
shows an example of a controllable current generator
150
suitable for use in the interpolating ADC stage
100
of
FIG. 1
a
. An input transistor
151
and a constant current sink
152
are connected in series between power supply lines
154
,
156
, a connection between transistor
151
and current sink
152
providing a current output Iout
158
. Input transistor
151
has a control voltage Vc applied to its gate connection to provide a controlled, unipolar current equal to the sum of the output current Iout and the current through the constant current sink
152
. Thus the output current may be of either polarity depending upon the magnitude of the controlled unipolar current through input transistor
151
. For a given input control voltage Vc the output current (or the outputs of a plurality of matched controllable current generators) can be scaled by scaling the dimensions of input (MOS) transistor
151
. The current sink
152
is preferably scaled in the same ratio to maintain a constant “zero current” point. In this way a plurality of differently-scaled, matched controllable current generators may be arranged to have zero output current for substantially the same input control voltage, and thus to provide zero output current substantially simultaneously.
Where transistors comprising elements
112
a
and
112
b
have the same physical size the current on line
118
a
is substantially the same as the current through element
112
a
. The sizes of transistors comprising elements
112
c, d, e
are reduced to 0.75×, 0.5× and 0.25×that of element
112
b
so that respective currents of 0.75×, 0.5× and 0.25× the output current from transconductance amplifier
104
are provided on lines
118
b
,
118
c
and
118
d
. Generally current mirror
112
is fabricated on an integrated circuit so that the transistors comprising the current mirror are matched. Current mirror
114
likewise comprises elements
114
a-e
, for example bipolar or FET transistors, and operate
Dickstein , Shapiro, Morin & Oshinsky, LLP
Nguyen Khanh Van
Wolfson Microelectronics, Ltd.
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