Transaction scheduling for a bus system in a multiple speed...

Multiplex communications – Communication techniques for information carried in plural... – Assembly or disassembly of messages having address headers

Reexamination Certificate

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Reexamination Certificate

active

06771664

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to the field of data communication in a digital system. More particularly, the present invention relates to host controllers and hubs used to transfer information on a bus.
BACKGROUND OF THE INVENTION
A computer or similar device typically has a bus that connects peripherals to the computing system. Sometimes a hub or multiple hubs may be placed in between the peripheral and the computing system (host). A hub provides a fan-out capability by allowing multiple peripherals to be connected to the hub which is in turn connected to the host or a daisy-chain of hubs one of which is ultimately connected to the host. Some of the peripherals operate at a high data rate and some operate at a low data rate. Due to a variety of advances (e.g., computing power) in computers (hosts) and peripherals, the data rates at which some peripherals operate has increased significantly. The increase in data rates cannot be met using existing bus standards. For example, the relative difference between the highest data rate peripheral on a bus and the lowest data rate peripheral on a bus has increased to the point that existing solutions for allowing high data rate peripherals and low data rate peripherals to co-exist on the same bus are typically not very efficient. Additionally, existing solutions for allowing hosts to communicate with both advanced, high data rate devices and legacy, low data rate devices usually require the host and/or hub to be relatively complex and costly.
The increased demand for high data rates, as described above, cannot be met using existing buses nor using the bus architecture and protocols of existing buses. For example, the Universal Serial Bus (USB) Specification Revision 1.1, Sep. 23, 1998, (USB Standard) is limited to a full-speed data rate of 12 Mb/s (megabits per second) and a low-speed data rate of 1.5 Mb/s. Examples of relatively high data rate peripherals, include cameras, compact disc players, speakers, video cameras, microphones, video display devices, and scanners among other devices. Unfortunately, many of these devices have data rate requirements that exceed the data rates supported by USB. For example, a video display device can have a data rate in excess of 20 Mb/s.
Existing solutions for allowing high data rate peripherals and low data rate peripherals to co-exist on the same bus are typically not very efficient when used for buses whose ratio of the highest data rate supported on the bus to the lowest data rate supported on the bus is relatively large. Examples of low data rate peripherals, include mice and joy-sticks that need to co-exist along with the high data-rate peripherals. A mouse typically has a data rate significantly less than 0.1 Mb/s. When the ratio of the highest data rate to the lowest data rate is relatively small, solutions such as speed-shifting and non-multiplexed store-and-forward transactions are tolerable despite their relative inefficiency.
In USB, for example, speed-shifting refers to a host communicating at a low-speed with low data rate peripherals and alternatively at full-speed with high data rate devices (speed-shifting). Unfortunately, the amount of data actually transmitted over the bus (effective throughput) is less than that achievable by limiting the bus to full-speed transactions. Speed-shifting is also employed by “Firewire” or Institute of Electrical and Electronics Engineers (IEEE) Standard 1394 for a High Performance Serial Bus, 1995. Even though IEEE 1394 supports multiple data rates, up to 400 Mb/s, speed-shifting and the relatively high cost of Firewire make it an undesirable technology. The inefficiency of Firewire can be relatively severe when speed-shifting occurs in communicating between a 0.1 Mb/s mouse and a 20 Mb/s video display device.
Non-multiplexed store and forward transactions occur when a host (1) transmits at a high data rate a packet to a store-and-forward hub, (2) waits for the hub to forward at the low data rate the packet to the peripheral, (3) waits for the peripheral to respond at the low data rate to the hub, and (4) receives from the hub at a high data rate the peripheral's response to the packet. When the ratio of the highest data rate supported on the bus to the lowest data rate supported on the bus is relatively large, this co-existence solution may also result in a low effective throughput or bandwidth because of the time wasted in waiting for the hub to forward the packet at the low data rate and for the peripheral to respond at the low data rate.
As described above, existing buses are not capable of providing the high data rates required by modem peripherals. Additionally, existing solutions that allow high data rate peripherals and low data rate peripherals to co-exist on the same bus typically result in the bus having inefficient performance. Consequently, it is desirable to provide the high data rates required by modem peripherals, and efficient solutions allowing high data rate devices and low data rate devices to co-exist on the same bus.
SUMMARY OF THE INVENTION
According to an embodiment of the invention a method for communicating data using a hub is described. The method includes determining a first estimated unused capacity left in a first frame in which a second transaction is to be performed between a hub and an agent. The method then includes determining an amount of a first data that can fit into the estimated unused capacity and that is to be sent to the hub during a first transaction and then sent by the hub to the agent during the second transaction. The method also includes sending the first data to the hub during the first transaction.


REFERENCES:
patent: 5564114 (1996-10-01), Popat et al.
patent: 5630174 (1997-05-01), Stone, III et al.
patent: 5870567 (1999-02-01), Hausauer et al.
patent: 5936967 (1999-08-01), Baldwin et al.
patent: 6067591 (2000-05-01), Howard et al.
patent: 6069872 (2000-05-01), Bonomi et al.
patent: 6098134 (2000-08-01), Michels et al.
patent: 6098137 (2000-08-01), Goodrum et al.
patent: 6104708 (2000-08-01), Bergamo
patent: 6266731 (2001-07-01), Riley et al.
patent: 6515965 (2003-02-01), Hou et al.
U.S. Ser. No. 09/361,677; by John Garney et al. filed Jul. 27, 1999. Patent Pending. Title: Transaction Scheduling For A Bus System.
U.S. Ser. No. 09/361,677; by John Garney et al. filed Jul. 27, 1999. Current Pending Claims. Patent Pending. Title: Transaction Scheduling For A Bus System.
U.S. Ser. No. 09/362,991; by John Garney et al. filed Jul. 27, 1999. Patent Pending. Title: Split Transaction Protocol For A Bus System.
U.S. Ser. No. 09/362,991; by John Garney et al. filed Jul. 27, 1999. Current Pending Claims. Patent Pending. Title: Split Transaction Protocol For A Bus System.
U.S. Ser. No. 09/461,625; by John Garney et al, filed Dec. 14, 1999. Patent Pending. Title: Tracking Transaction Status For A Bus System Providing Legacy Bus Compatibilty.

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