Multiplex communications – Channel assignment techniques – Only active channels transmitted
Reexamination Certificate
1998-11-02
2002-12-17
Kizou, Hassan (Department: 2662)
Multiplex communications
Channel assignment techniques
Only active channels transmitted
C370S235000, C370S395100
Reexamination Certificate
active
06496513
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a traffic priority control system for a concentration-type ATM (Asynchronous Transfer Mode) switch which is used in an ATM exchange, an ATM cross-connect apparatus, or the like, and more particularly to an ATM concentrator for achieving traffic priority control while preventing a reduction in the throughput of transmitted cells of low priority class with a plurality of output cell buffers for priority classes.
2. Description of the Prior Art
For ATM communications, an information signal such as an audio, video, or data signal is digitized and stored in the payload of an ATM cell that is 53 bytes long, and an ATM traffic composed of the ATM cells is transmitted.
Audio, video, and data signals have different information rates (i.e., transmission bands) and different allowable transmission delay times. Therefore, users of these signals pose different requirements for the qualities of services (QoS) of ATM networks, such as transmission band assurances and transmission delay assurances, with respect to audio, video, and data traffic. For example, users want to reduce any transmission delay for audio and video traffic because if the transmission delay were too large, audio and video signals reproduced from ATM cells at a receiver would be unnatural to the users. On the other hand, low-rate data traffic keep their qualities from being lowered even when their transmission delay is somewhat large.
There is known a priority control system for controlling the transmission of information signals depending on a number of quality classes established with respect to different requirements for transmission delays and transmission bands of the information signals. According to the priority control system there are established, more specifically, quality classes for traffic comprising ATM cells of information signals, and one of the quality classes is assigned to an ATM cell depending on connection numbers such as VPI (Virtual Path Identifier) and VCI (Virtual Connection Identifier) and a CLP (Cell Loss Priority) bit that are contained in the header of the ATM cell. In a buffer of an ATM exchange or an ATM cross-connect, the quality class of the ATM cell for a connection is determined depending on the VPI, the VCI, and the CLP bit in the header of the arrived ATM cell, and the ATM cell is controlled for transmission depending on the determined quality class.
One example of such a priority control system will be described below with reference to FIG.
1
.
FIG. 1
shows an ATM cell buffer system having a single input highway and a single output highway. There are established two quality classes with respect to transmission delays, i.e., a high priority class (class
1
) and a low priority class (class
2
) for ATM cells. The ATM cell buffer system has a cell buffer
33
for storing ATM cells of the high priority class and a cell buffer
34
for storing ATM cells of the low priority class. The cell buffers
33
,
34
are connected to the input highway through respective connection filters
31
-
1
,
31
-
2
. The connection filters
31
-
1
,
31
-
2
refer to the VPI, the VCI, and the CLP bit of each ATM cell that has arrived from the input highway to determine the quality class of each ATM cell, and transfers valid cells of determined quality classes to the respective cell buffers
33
,
34
. For example, if an ATM cell that has arrived at the connection filter
31
-
1
is of the high priority, then the connection filter
31
-
1
stores the ATM cell in the cell buffer
33
, and if an ATM cell of the low priority has arrived, then the connection filter
31
-
2
stores the ATM cell in the cell buffer
34
. The cell buffers
33
,
34
have respective output terminals connected to a readout controller
32
which reads ATM cells from the cell buffers
33
,
34
.
According to a process of determining a sequence to read ATM cells in the readout controller
32
, as disclosed in Japanese laid-open patent publication No. 4-220834 (JP, A, 04220834) (column 7, lines 9 to 14), for example, the readout controller
32
attempts to read ATM cells from the cell buffer
33
for the high priority class, and if the number of ATM cells stored in the cell buffer
33
is zero, then the readout controller
32
attempts to read ATM cells from the cell buffer
34
for the low priority class. Such a process is referred to as full priority control. The full priority control is advantageous in that it allows the readout controller
32
to carry out a simple control process and is applicable to high-speed circuits.
An ATM concentrator will be described below. An ATM concentrator is an ATM switch for connecting a plurality of input highways to a fewer number of output highways than the input highways. An (m×n−n) ATM concentrator connects (m×n) input highways to n output highways. For example, as disclosed in Japanese laid-open patent publication No. 7-66827 (JP, A, 07066827) (see
FIG. 1
thereof), if an ATM exchange or an ATM cross-connect which has (m×n) input highways and (m×n) output highways is to be constructed with m basic modules having n input highways and n output highways and a single connection module, an (m×n−n) ATM concentrator is used for connecting (m×n) input highways to n output highways in the connection module.
FIG. 2
shows a conventional (m×n−n) ATM concentrator. An (m−1) selector serves to select one of m highways, and n pieces of (m−1) selectors
11
-
1
to
11
-n are connected to (n×m) input highways. A counter
12
is connected to control the (m−1) selectors
11
-
1
to
11
-n to select one of the input highways. Output signals from the (m−1) selectors
11
-
1
to
11
-n are supplied through respective connection filters
36
-
1
to
36
-n to a routing decision circuit
13
. The routing decision circuit
13
has output terminals connected to a routing network
14
of an (n×n) Banyan switch. The routing network
14
has n output terminals connected through respective output cell buffers
35
-
1
to
35
-n, each comprising an FIFO (First-In First-Out) memory, to n output highways.
Input signals from the (n×m) input highways are multiplexed into n signals, whose speed is m times the speed of the input signals, by the (m−1) selectors
11
-
1
to
11
-n. Specifically, if the speed of an input signal from an input highway is represented by V, then the speed of a signal outputted from an (m−1) selector is represented by mV. Based on a signal generated by the counter
12
, the (m−1) selectors
11
-
1
to
11
-n are operated in synchronism each other for synchronized multiplex timing. The n multiplexed signals are delivered to the connection filters
36
-
1
to
36
-n, respectively, which refer to the VPI, the VCI, or the CLP bit in the header of each ATM cell to decide whether the ATM cell is a valid cell of a passing connection to pass through the ATM concentrator or not. If the ATM cell is a valid cell of a passing connection, then the connection filters
36
-
1
to
36
-n send the valid cell to the routing decision circuit
13
. If the ATM cell is not of a passing connection or it is an invalid cell of a passing connection, then the connection filters
36
-
1
to
36
-n write the ATM cell over an idle cell or an invalid cell.
The routing decision circuit
13
and the routing network
14
serve to hold sequences of arrival of valid cells from the same input highways and store valid cells uniformly in the output cell buffers
35
-
1
to
35
-n for thereby preventing valid cells from concentrating on and hence overflowing some of the output cell buffers
35
-
1
to
35
-n. Based on the known function of the Banyan switch for sorting a monotonous signal string into a continuous signal string without blocking, the routing decision circuit
13
and the routing network
14
shift and output valid cells, one by one, successively from highways of smaller numbers, and shift effective cells arriving in a next ce
Dickstein, Shapiro, Morin & Oshinsky L.L.P.
Kizou Hassan
Spafford Tim
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