Tracking control pulse generation for variable frame rate CCD se

Details Tracking control pulse generation for variable frame rate CCD se Tracking control pulse generation for variable frame rate CCD se

1992-03-09

1994-06-14

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307511, 307518, 307603, 328 58, H03K 3017

Patent

active

053213157

ABSTRACT:
Reset, clamp, and sample pulses for a CCD sensor for electronic imaging applications are generated which have their leading edges delayed with respect to the leading edges of corresponding pixel clock pulses by substantially constant proportions of the pixel clock period independently of pixel frequency. To do this, a first auxiliary 50 percent duty cycle pulse train is generated having a frequency 4 times the pixel frequency. A divide by 4 counter receives the first auxiliary train and produces both the pixel clock itself and a second auxiliary 50 percent duty cycle pulse train having a frequency twice the pixel frequency. A 3 to 8 line decoder receives the pixel clock and both auxiliary trains to produce eight separate trains of pulses having the pixel frequency and a substantially 12.5 percent duty cycle. Each of the eight separate trains has the leading edge of its pulses delayed by substantially an eighth of the pixel clock period from the leading edge of the pulses of a different one of the eight separate trains. Different ones of the eight separate rains are selected to form the desired trains of reset, clamp, and sample pulses.

REFERENCES:
patent: 4004162 (1977-01-01), Kato et al.
patent: 4414637 (1983-11-01), Stanley
patent: 4423383 (1983-12-01), Svendsen
patent: 4623846 (1986-11-01), La Macchia
patent: 4683495 (1987-07-01), Brock
patent: 4710721 (1987-12-01), Camus
patent: 4891828 (1986-01-01), Kawazoe
patent: 4998025 (1991-03-01), Watanabe
patent: 5077529 (1991-12-01), Ghoshal
patent: 5265063 (1993-11-01), Kogure

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