Track and hold circuit

Details Track and hold circuit Track and hold circuit

2000-10-27

2003-01-07

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S537000, C327S096000

Reexamination Certificate

active

06504406

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a track and hold circuit and, more particularly, to a track and hold circuit with high precision and low distortion suitable for a front end of an analog-to-digital converter.
2. Description of the Related Art
A track and hold circuit is one of basic analog circuits used as, for example, a front end of an analog-to-digital converter and is used to sample the values of signals, continuously changing with time, at discrete time intervals. There are three factors in distortion of this track and hold circuit. These factors will be classified below using the most basic conventional example of a track and hold circuit shown in FIG.
4
.
(A) Variation in the Charging Time of a Hold Capacitor in the Track Mode
A track and hold circuit shown in
FIG. 4
consists of two amplifiers
101
and
102
, a MOS transistor
103
operating as an FET switch, a hold capacitor
104
, and a clock source
105
. A bulk terminal of the MOS transistor
103
is connected to a common potential point (ground). Base resistance Ron with the MOS transistor
103
in the ON state depends on the gate driving voltage V&PHgr;, drain input voltage V
in
, and threshold voltage V
th
of the MOS transistor
103
and the following relationship exists between them:
R
on
=1/{&bgr;(
V
&PHgr;
−V
in
−V
th
)}  (1)
Where &bgr; is a constant depending on production process and &bgr;=&mgr;C
ox
W/L (&mgr;: mobility, C
ox
: gate oxide capacitance per unit area, W: gate width, L: gate length).
Therefore, when V
in
varies, R
on
also varies. This leads to variations in a time constant for charging the hold capacitor
104
given by R
on
×C
H
. The dependence of the on-state resistance R
on
of the MOS transistor
103
on signals, that is to say, the dependence of the on-state resistance R
on
of the MOS transistor
103
on V
in
which varies as a matter of course necessarily causes variations in the charging time of the hold capacitor and thus results in harmonic distortions.
(B) Electric Charge Injection at the Time of Mode Transition
As shown in
FIG. 5
, moreover, electric charges stored at the gate of the MOS transistor
103
are released at the time of the transition from the track mode to the hold mode. That is to say, electric charge Q
1
injected into the gate of the MOS transistor
103
when the MOS transistor
103
is in the ON state is released when it becomes the OFF state. Furthermore, electric charge Q
2
stored by parasitic capacity C
gs
between the gate and the source of the MOS transistor
103
is also released when it becomes the OFF state. The flow of electric charge Q
1
and Q
2
into the hold capacitor at the time of the MOS transistor
103
becoming the OFF state could cause harmonic distortions. It is known that Q
1
and Q
2
can be calculated by the following formulas:
Q
1
=−
C
ox
A
(V
&PHgr;
−V
in
−V
th
)  (2)
where C
ox
is the gate oxide capacitance per unit area of the MOS transistor
103
, as stated above; A is the gate area of the MOS transistor
103
; V
&PHgr;
is the clock voltage; V
in
is the drain input voltage, as stated above; and gate voltage V
th
is the threshold voltage of the MOS transistor
103
, as stated above.
Q
2
=−
C
gs
(
V
in
+V
th
)  (3)
where C
gs
is the capacitance between the gate and the source of the MOS transistor and V
th
is the threshold voltage, as stated above. Furthermore, C
gs
has dependence on the input voltage given by the following formula:
C
gs
=C
gs0
/{1−(V
&PHgr;
−V
in
−V
th
)/&psgr;
0
}
½
  (4)
where &psgr;
0
is what is called built-in potential and C
gs0
represents the value of C
gs
with V
gs
=0.
Therefore, Q
1
and Q
2
both depend on the input signal voltage V
in
, which could cause harmonic distortions. Q
2
particularly depends on V
in
non-linearly.
Trials for reducing distortions caused by variations in input voltage have been made. One of them is to reduce the dependence of the on-state resistance on input signals by applying a gate higher driving voltage or by adopting the structure of a CMOS switch. With the former method, a high driving voltage will lead to an increase in electric charges being released at the transition. Furthermore, the use of high driving voltages is contrary to a tendency toward the use of lower voltages in recent circuit designs. The latter method requires a high-speed PMOS and has the problem of a shift in transition timing due to a difference in V
th
.
Another attempt for changing gate voltages according to the level of input signals has been made. For example, see an application note AN301 of Siliconix Department of TEMIC Semiconductor Inc. (dated Mar. 10, 1997) or Japanese Patent No. 2833070 (Japanese Pat. Laid-open No. Heisei 3-219724). However, such circuit structure requires a voltage source of 10-15 volts. It therefore can be used for, for example, measurement instruments, but it is not suitable for system LSIs in which operating voltage has to be low. Moreover, driver circuits become complex.
The reduction of electric charge injection by a dummy switch has also been considered (see Japanese Pat. Laid-open No. Heisei 10-312698, for example). With this method, another MOS transistor is located between the above MOS transistor
103
and the amplifier
102
on the output side or the ground in order to absorb at least part of electric charges flowing into the hold capacitor. But this requires fine control of the drive timing of the additional MOS transistor. In addition, the more essential problem is that it is difficult to treat electric charge injection quantitatively.
SUMMARY OF THE INVENTION
Considering problems with the above related art, an object of the present invention is to provide a track and hold circuit which operates at a lower voltage and can reduce distortions in hold waveforms.
The present invention reduces distortions of a track and hold circuit by biasing the bulk or substrate potential of a MOS transistor switch with a certain voltage.
The present invention provides a track and hold circuit comprising a MOS transistor switch and a hold capacitor in which a certain voltage is applied to the bulk potential of the MOS transistor switch. Furthermore, the track and hold circuit may comprise an amplifier. A terminal of the hold capacitor which is connected to the MOS transistor switch is connected to the input of the amplifier, and the output from the amplifier forms that of the track and hold circuit. In addition, a buffer amplifier may be connected between the MOS transistor switch and the input end of the track and hold circuit.
The present invention also provides a track and hold circuit comprising an amplifier whose inverted input terminal receives input signals in the track mode, a hold capacitor one end of which connects electrically with the output of the amplifier and the other end of which becomes electrically connected to the inverted input terminal of the amplifier in the hold mode, a first MOS transistor switch connected between the other end of the hold capacitor and the inverted input terminal, a second MOS transistor switch located between the other end of the hold capacitor and a common potential point, a third MOS transistor switch connected between an input signal terminal and the inverted input terminal, a fourth MOS transistor switch connected between the input signal terminal and the common potential point, and a constant voltage circuit connected to bulk terminals of the first to fourth MOS transistor switches.
In these track and hold circuits according to the present invention, a constant voltage circuit may consist of a memory and a digital-to-analog converter which receives a digital signal from the memory.


REFERENCES:
patent: 3701059 (1972-10-01), Nyswander
patent: 3820033 (1974-06-01), Iwata
patent: 5324995 (1994-06-01), Yee
patent: 5517140 (1996-05-01), Hatsuda
patent: 6265911 (2001-07-01), Nairn
patent: 0875904 (1998-1

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