Trace design to minimize electromigration damage to solder...

Details Trace design to minimize electromigration damage to solder... Trace design to minimize electromigration damage to solder...

2007-07-18

2010-02-09

Williams, Alexander O (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257SE23021, C257S774000, C257S775000, C257S789000, C438S612000

Reexamination Certificate

active

07659622

ABSTRACT:
A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology addresses the current distribution at the pad by dividing current carrying traces into a plurality of sub-traces with known resistances such that each sub-trace distributes a known amount of current to the pad of the integrated circuit. The multiple sub-traces connect to the pad and are placed to obtain a desired uniformity in the incoming current distribution. Width and/or length adjustments could be made to each of the plurality of sub-traces to obtain the desired resistances.

REFERENCES:
patent: 4654692 (1987-03-01), Sakurai et al.
patent: 5289036 (1994-02-01), Nishimoto
patent: 5461260 (1995-10-01), Varker et al.
patent: 5777486 (1998-07-01), Hsu
patent: 6504252 (2003-01-01), Matsunaga
patent: 6521996 (2003-02-01), Seshan
patent: 6818996 (2004-11-01), Mertol et al.
patent: 6825541 (2004-11-01), Huang et al.
patent: 7081405 (2006-07-01), Chien
patent: 7208843 (2007-04-01), Dauksher et al.
patent: 2003/0167632 (2003-09-01), Thomas et al.
patent: 2004/0004227 (2004-01-01), Tateishi
patent: 2004/0113261 (2004-06-01), Sunohara et al.
patent: 2005/0040527 (2005-02-01), Huang
patent: 2006/0043608 (2006-03-01), Bernier et al.
patent: 2006/0186539 (2006-08-01), Dauksher et al.

Affiliated with

Also associated with

Rating

Trace design to minimize electromigration damage to solder... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Trace design to minimize electromigration damage to solder..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trace design to minimize electromigration damage to solder... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4217113