Trace design to minimize electromigration damage to solder...

Details Trace design to minimize electromigration damage to solder... Trace design to minimize electromigration damage to solder...

2007-08-07

2007-08-07

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S789000, C438S612000

Reexamination Certificate

active

11047887

ABSTRACT:
A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology addresses the current distribution at the pad by introducing an intermediate trace routing design between the current delivering trace and the pad that distributes the inflow of current from the trace to multiple points of entry on the pad. The intermediate trace routing design includes an outer trace channel connected to the current delivering trace. A plurality of conductive trace leads connect the outer trace channel to the pad. Preferably, each of the plurality of conductive trace leads is characterized by a respective trace impedance so as to distribute equal current flow through each of the leads to the pad.

REFERENCES:
patent: 4654692 (1987-03-01), Sakurai et al.
patent: 5289036 (1994-02-01), Nishimoto
patent: 5461260 (1995-10-01), Varker et al.
patent: 6818996 (2004-11-01), Mertol et al.

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