Totally self-aligned transistor with polysilicon shallow trench

Details Totally self-aligned transistor with polysilicon shallow trench Totally self-aligned transistor with polysilicon shallow trench

1998-06-24

2000-10-03

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With polycrystalline semiconductor isolation region in...

257506, 257508, 257618, 257623, H01L 2900, H01L 2906

Patent

active

061277177

ABSTRACT:
A totally self-aligned transistor with shallow trench isolation. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. Channel dopant deposited in the gate area is also self-aligned to the gate of the transistor.

REFERENCES:
patent: 5494837 (1996-02-01), Subramanian et al.
patent: 5565697 (1996-10-01), Asakawa
patent: 5859466 (1999-01-01), Wada
patent: 5880508 (1999-03-01), Wu
Article entitled, "Spatially Confined Nickel Disilicide Formation at 400.degree. C. On Ion Implantation Preamorphized Silicon" Author: Erokin et al.

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