Total ionizing dose suppression transistor architecture

Details Total ionizing dose suppression transistor architecture Total ionizing dose suppression transistor architecture

2007-03-16

2010-06-15

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

With shielding

C257S921000, C257SE23114, C438S953000

Reexamination Certificate

active

07737535

ABSTRACT:
A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the metal structure to the lowest potential voltage to steer the charge away from the critical field (inter-device) and keeps non-local charge from migrating to the “birds-beak” region of the transistor, preventing further charge buildup. The “end cap” structure seals off the “birds-beak” region and isolates the critical area. The critical area charge is source starved of an outside charge. Outside charge migrating close to the induced field is repelled away from the critical region. The architecture is further extended to suppress leakage current between adjacent wells biased to differential potentials.

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