Total error multiplier for optimizing read/write channel

Details Total error multiplier for optimizing read/write channel Total error multiplier for optimizing read/write channel

2001-06-29

2004-05-04

Hudspeth, David (Department: 2651)

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Head amplifier circuit

C360S051000, C360S045000, C360S065000

Reexamination Certificate

active

06731443

ABSTRACT:

BACKGROUND
Computer hard disk drives, also known as fixed disk drives or hard disk drives, have become a de facto data storage standard for computer systems. Their proliferation can be directly attributed to their low cost, high storage capacity and reliability, in addition to wide availability, low power consumption, fast data transfer speeds and decreasing physical size.
Disk drives typically include one or more rotating magnetic platters encased within an environmentally controlled housing. The hard drive may have several read/write heads that interface with the magnetic platters. The disk drive may further include electronics for reading and writing data and for interfacing with other devices. The electronics are coupled with the read/write heads and include circuits to control head positioning and to generate or sense electromagnetic fields on the platters. The electronics encode data received from a host device, such as a personal computer, and translate the data into magnetic encodings, which are written onto the platters. When data is requested, the electronics locate the data, sense the magnetic encodings, and translate the encodings into binary digital information. Error checking and correction may also be applied to ensure accurate storage and retrieval of data.
The read/write heads detect and record the encoded data as areas of magnetic flux. The data are encoded by the presence or absence of a flux reversal between two contiguous areas of the platter. Data may be read using a method known as “Peak Detection” by which a voltage peak imparted in the read/write head is detected when a flux reversal passes the read/write head. However, increasing storage densities, requiring reduced peak amplitudes, better signal discrimination and higher platter rotational speeds are pushing the peaks in closer proximity. Thus, peak detection methods are becoming increasingly complex.
Advancements in read/write heads and in the methods of interpreting magnetic encodings have been made. For example, magneto-resistive (“MR”) read/write heads have been designed with increased sensitivity and increased signal discrimination. In addition, technology known as Partial Response Maximum Likelihood (“PRML”) has been developed. PRML disk drives function based an algorithm implemented in the disk drive electronics to read analog waveforms generated by the magnetic flux reversals. Instead of looking for peak values, PRML based drives digitally sample the analog waveform (the “Partial Response”) and carry out advanced signal processing techniques to determine a most-likely bit pattern represented by the wave form (the “Maximum Likelihood”). PRML technology tolerates more noise in the magnetic signals, permitting use of lower quality platters and read/write heads, which also increases manufacturing yields and lowers costs.
With hard drives typically differentiated by factors such as cost/unit of storage, data transfer rate, power requirement, and form factor (physical dimensions), there is a need for enhanced hard drive components which prove cost effective in optimizing set-up time, storage capacity, operating speed, reliability and power efficiency. An example of an area includes PRML electronics used to calibrate and tune the PRML read/write channel to the read/write head. The process of calibrating and tuning the PRML read/write channel with the read/write head, often referred to as “channel margining,” is performed when the read/write head is combined with the read/write channel. During channel margining, variable parameters of the read/write channel are adjusted to generate an optimal bit-error rate for the hard disk drive and read/write channel combination.
During channel margining, channel parameters are iteratively varied through an exhaustive matrix to determine the best bit-error rate for the read/write head and read/write channel combination. After channel margining has advanced through several stages, the hard disk drive may be operating at a bit-error rates requiring significant time to detect the bit errors. Methods used to reduce time inject artificial interference, or additive white Gaussian noise (AWGN), to the read/write channel result. These methods result in a set of channel parameters that are not optimal for low bit-error rate operation.
Accordingly, there is a need for reducing the time and resources for channel margining, while providing a low bit-error rate.
SUMMARY
A method and apparatus to optimize a bit error rate for a partial response, maximum likelihood (“PRML”) read/write channel is disclosed. The magnetic recoding channel may include a channel margining circuit configured to carry out the channel margining method herein disclosed. The channel margining circuit derives an interference signal inherent with the bit error rate inherent with the bit error of the read/write channel. The interference signal may be amplified by a variable scaling factor. The variable scaling factor may be adjusted to provide artificial enhancement or degradation of a signal processed by the read/write channel. The scaled interference signal may be combined with a selected test data pattern and provided to a Viterbi detector circuit of the read/write channel. In an embodiment, the read/write channel is a partial response, maximum likelihood (“PRML”) based read/write channel.
An embodiment for the channel margining circuit may include a bit pattern generator circuit, a first summing circuit, a scaling circuit, and a second summing circuit. The components of the channel margining circuit are configured to provide a variably amplified interference signal to a Viterbi detector circuit of read/write channel. The interference signal is associated with the total error of the read/write channel.
The bit pattern generator is operative to generate a digital signal having a selected pattern at a bit pattern generator output. A typical selected test pattern generated by the bit pattern generator is a parity compliant code. The selected pattern may be, for example, a pseudo random binary sequence (“PRBS”) data pattern generated by linear feedback shift register (“LFSR”).
The first summing circuit includes a first input, a second input, and an output. The first input may be coupled with the bit pattern generator output. The first input is configured to receive the digital signal from the bit pattern generator. The second input is configured to receive a processed binary data signal. The processed binary data signal is associated with data read from a magnetic data storage medium and processed by the read/write channel. The summing circuit is configured to generate an interference signal. The interference signal may be provided at the first summing circuit output. In an embodiment, the interference signal is associated with a difference between the digital signal provided at the first input and the processed binary data signal at the second input.
The scaling circuit includes an input that may be coupled with the first summing circuit via the first summing circuit output. The scaling circuit is configured to generate a scaled interference signal at the scaling circuit output. The scaling circuit is further configured to amplify the interference signal by a variable scaling factor. The variable scaling factor may be adjusted to provide a desired level of enhancement or degradation of a signal processed by the read/write channel.
The second summing circuit includes a first input, a second input, and an output. The first input is configured to receive the scaled interference signal from the scaling circuit output. The second input may be coupled with the bit pattern generator output. The second input is configured to receive the digital signal generated by the bit pattern generator. The second summing circuit combines the digital signal and the scaled interference signal. The combined signals are provided at the second summing circuit output, which defines an output for the channel margining circuit.
An embodiment of a method of optimizing a bit-error rate for a read/write channel includes: reading a known

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