Torus routing chip

Details Torus routing chip Torus routing chip

1986-12-19

1990-06-12

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 8512, H04J 326

Patent

active

049339338

ABSTRACT:
A deadlock-free routing system for a plurality of computers ("nodes") is disclosed wherein each physical communication channel in a unidirectional multi-cycle network is split into a group of virtual channels, each channel of which has its own queue, one at each end. Packets of information traversing the same physical channel are assigned a priority as a function of the channel on which a packet arrives and the node to which the packet is destined. The packet's priority is always increasing as it moves closer and closer to its destination. Instead of reading an entire packet into an intermediate processing node before starting transmission to the next node, the routing of this invention forwards every flow control unit (flit) of the packet to the next node as soon as it arrives. The system's network is represented as a dependency graph, which graph is re-ordered to be cycle free. The resulting routing function of the cycle free channel dependency graph is rendered deadlock-free, and the system's cut-through routing results in a reduced message latency when compared under the same conditions to store-and-forward routing.

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patent: 4742511 (1988-05-01), Johnson
patent: 4763319 (1988-08-01), Rozenblit
patent: 4797882 (1989-01-01), Maxemchuk

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