Topography processor system

Image analysis – Image enhancement or restoration – Image filter

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

37, 37, C714S025000, C714S046000

Reexamination Certificate

active

06233361

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to a topography processor system.
ANALYSIS OF BACKGROUND ART AND SUMMARY OF INVENTION
The advent of three dimensional optical mapping systems, based on correlated information from a phased array of image sensors (CCD or equivalent) sets new levels of complexity in system architecture design. This complexity poses considerable problems not only during experimental development and integration but also sets minimum diagnostic requirements for “first line” monitoring of a production equipment's status. The purpose of this invention is the combination of features namely, the architecture of a frame rate topography processor system, use only of such a system's sufficient control, data and address highways, and the introduction of end to end non interruptive graphic macro diagnostic techniques to allow “first line” system GO/NOGO decisions to be reached without the need for an extensive second layer microscopic BITE, or the use of additional external test equipments. These capabilities provide non interruptive visual, augmented visual or automatic visual diagnostic determination of correct end to end system internal parameter, or combined parameter performance characteristics.
The division between the embodiment of functionality in the hardware or software of an optical typography processing systems is dictated by the target applications required maximum real time response. Using frame stores and time dilation many systems take advantage of processors, operating within Von Neumann architectures, to identify vectors of particular attributes, and correlate such vectors between their different perspective images in the calculation of the system relative range to elements of topographical detail otherwise referred to as image detail range decompression.
Such systems benefit from the reliability of today's digital technology and the flexibility afforded by programming languages. The comfort afforded by high level software exacts a price for their inherent expansion factors in the serial execution speed of such processes, and the reduced visibility of the target machine process mapping, and therefore of its executed performance. Faster execution and visibility supported by low level software design alas remains a specialist domain in whose absence reliability and maintainability issues often arise.
For a modest system comprising three virtual imager systems with operating bandwidths of around 5 mHZ and utilising vectors of two different attributes, then it is arguable that for complete image detail range decompression at the image sensor frame rate, would necessitate vector intercepts to be calculated at an effective rate of around 300 mHZ. The latency of such processes embedded in software will currently generally considerably exceed that of a frame period. Diagnostic monitoring of software performance usually necessitates a combination of offline postmortem scrutiny, and or the use of monitoring by utility and trace systems. The information from such processes is generally microscopic and representative of implementation computational anomalies, or possible evidence of a failure in the passing of control or data. In any event the provision of diagnostic information, and or its recovery from a system introduces overheads to the target application, in respect of application non essential, or additional external equipments, and or in respect of the latency of their associated serial processing techniques which further takes the system out of its normal operational envelope, and almost certainly further away from frame rate execution.
The identification and rectification of hardware failures tends to fall into a hierarchy of approaches. Systems with integrated BITE start of day, or continuous BITE often allow at the “first line” timely identification of system malfunctions. The use of such techniques to identify GO/NOGO situations support high levels of overall system operability. At the “second line” intermediate level, equipments isolated from a system lend themselves to analysis by dedicated test equipments, and or board swapping to rectify failures. For localized functional anomalies, “third line” specialist monitoring at board level supports rectification of failed components.
Characteristic of all these techniques for both software and hardware is that they address microscopic detail in a system's performance, whose interpretation may provide evidence, in specific contexts, of the causal mechanisms for failure of macroscopic functionality. However many of the techniques tend to clinically isolate the functionality under scrutiny, and therefore isolate some faults from the operational envelope in which they occur. The purpose of non interruptive graphic macro diagnostics is to achieve through envelope testing, the rapid identification of system functional GO/NOGO indications enabling if necessary part, or whole system removal for “second” or “third line” testing.
For what may recently be considered as a complex system in which an interprocessor link supports 1000 parameters, optimistically, for process completion within a frame period, image detail range decompression processing systems need to process two to three orders of magnitude more data, realistically 300,000 parameters within the frame period. A topographical mapping system architecture described later capable of correlating all of the imaged generic pattern data within the frame period of a phased image sensor array, comprising a minimum of three virtual image sensors operating around 5 mHZ, has overall system data requirements in the order of 600 Million units (such systems tend to operate with mixed word lengths) of partitioned online RAM. An experimental implementation of an element of such a processing system comprising a single line scan processor necessitated some 60 Euro cards containing in all some 700 integrated circuits of which about 10% were VLSI and a guesstimated 20,000 pin to pin threads. To support continuous processing of data at the frame rate some 30 simultaneous parallel address processes, in support of the machines inherent multiple address capabilities, operate within each line scan processing element at the machine's clock rate.
Whilst physically such an experimental system lends itself technologically to miniaturization the complexity remains, and therefore also a clear requirement not only for the use of diagnostics in support of system development and integration, but also in support of the use of such production equipments. Whilst many systems benefit from a functionally integrated level of BITE allowing the stimulation and monitoring of system control and data threads, the introduction of a second layer of circuitry here poses immediate problems of scale. Further in practical terms the cost of such an integration for a “microscopic” diagnostic capability suggests a different approach to GO/NOGO system integrity is better sought, allowing the development of cheaper special to type “second” and “third line” test equipments.
Optical topography processor systems are by nature concerned with imaged data, which we (humans) can quickly asses. In the context of diagnostics, graphic macro diagnostics allow such human visual, or augmented visual macroscopic assessment of end to end internal system performance, or the automatic assessment of system performance based on such visual patterns.
For a topography processor system operating synchronously at the frame rate of an image sensor, advantage may be taken of a graphic macro diagnostic capability in the analysis of internal as well as overall system performance characteristics. Equally for such a system with internal asynchronous functionality, executing and completing within a frame period, then for a defined apriori system drive such asynchronous functionality may also be considered to be operating in a synchronous fashion, and therefore also lends itself to the same graphic macro diagnostics techniques. An example of an analogous capability is the television test card where m

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Topography processor system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Topography processor system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Topography processor system will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2457970

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.