Topography of CMOS microcomputer integrated circuit chip includi

Details Topography of CMOS microcomputer integrated circuit chip includi Topography of CMOS microcomputer integrated circuit chip includi

1989-06-20

1992-06-16

Lee, Thomas C.

Boots, shoes, and leggings

3642267, 364226, 3642327, 3642328, 3642329, 36423293, 3642702, 3642714, 364DIG1, G06F 106, G06F 108, G06F 1520, G06F 118

Patent

active

051231077

ABSTRACT:
The topography of a CMOS microcomputer chip includes first, second, third, and fourth consecutive edges, with chip control logic being located along the upper left edge. Five peripheral I/O port buffer circuits are located around the edge of the periphery of the chip, except for an eight bit peripheral output port located along the lower right edge and multiplexed with chip select outputs. The microcomputer includes an eight bit W65CO2S CMOS microprocessor, 192 bytes of SRAM, 4096 bytes of SROM, 22 edge interrupt inputs, 3 level-sensitive interrupt inputs, a UART, serial interface buffer for effectuating correction to a local area token passing network, four timers, and priority interrupt control circuitry. The topography is arranged to provide convenient connection of terminals of the microcomputer when it is used as a "core" of a larger computer system chip including an external memory system, a serial communication system, and an interrupt and I/O system. Static bus holding devices are connected to the memories on which I/O terminals are connected, and allow the microprocessor to interpret trinary logic states presented to the I/O port leads by external devices.

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