Topography for integrated circuit pattern recognition array

Details Topography for integrated circuit pattern recognition array Topography for integrated circuit pattern recognition array

1979-05-30

1981-09-01

Boudreau, Leo H.

Communications: electrical

Digital comparator systems

235463, G06K 714

Patent

active

042875072

ABSTRACT:
An integrated circuit for sequentially receiving a plurality of binary interval numbers, each representing the width of a time interval occurring during optical scanning of a bar coded label, includes first, second, third and fourth sequentially located edges forming a rectangle. The integrated circuit includes input logic circuitry for receiving and temporarily storing the binary interval numbers and a plurality of adders and shift registers for adding predetermined ones of the stored binary interval numbers and storing the resulting sums. The integrated circuit includes a plurality of comparators for comparing predetermined ones of the sums and stored sums to produce a plurality of intermediate signals. Encoding circuitry encodes predetermined ones of the intermediate logic signals to produce a digital character number representing a character scanned on the bar coded label and also includes output circuitry. The input logic circuitry is located adjacent to the first edge, and the plurality of comparator circuits are located generally along the third edge. The shift register and adder circuitry is generally located between the input logic circuitry and the plurality of comparator circuits. The encoder circuitry is located generally adjacent the fourth edge of the chip. The output circuitry is generally located adjacent the third edge.

REFERENCES:
patent: 4108368 (1978-08-01), Dobras
patent: 4140271 (1979-02-01), Nojiri et al.
patent: 4146782 (1979-03-01), Barnich
patent: 4147295 (1979-04-01), Nojiri et al.

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