Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2005-12-06
2005-12-06
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S243000, C438S244000, C438S386000, C438S387000, C438S743000, C438S756000, C438S692000
Reexamination Certificate
active
06972266
ABSTRACT:
A process and intermediate DRAM structure formed by providing a substrate having an array of trenches containing trench capacitors underlying vertical transistors in an array area separated by isolation trenches residing in both array and support areas. A top oxide nitride (TON) liner is deposited over array and support areas so as to directly contact the fill in the isolation trenches. An array top oxide (ATO) is then deposited directly over the TON liner such that during subsequent processing, the TON protects the isolation trench oxide from any divot opening etches while maintaining the isolation trench oxide height fixed during the ATO process. In further processing the intermediate structure, ATO and TON are removed from the support area only, leaving remaining portions of both ATO and TON only in the array area, such that the TON liner separates the ATO from the isolation trench fill.
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Divakaruni Ramachandra
Hummler Klaus M.
Capella Steven
Chen Eric B.
DeLio & Peterson LLC
Infineon Technologies North America Corp.
International Business Machines - Corporation
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