Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2007-11-13
2007-11-13
Soward, Ida M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S207000, C257S208000, C257S700000, C257S758000, C257S759000, C257S760000, C257S762000
Reexamination Certificate
active
11230004
ABSTRACT:
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
REFERENCES:
patent: 3823349 (1974-07-01), Dhaka et al.
patent: 4423547 (1984-01-01), Farrar et al.
patent: 4618878 (1986-10-01), Aoyama et al.
patent: 5055907 (1991-10-01), Jacobs
patent: 5060045 (1991-10-01), Owada et al.
patent: 5083187 (1992-01-01), Lamson et al.
patent: 5106461 (1992-04-01), Volfson et al.
patent: 5117272 (1992-05-01), Nomura et al.
patent: 5194928 (1993-03-01), Cronin et al.
patent: 5212403 (1993-05-01), Nakanishi et al.
patent: 5384488 (1995-01-01), Golshan et al.
patent: 5468984 (1995-11-01), Efland et al.
patent: 5501006 (1996-03-01), Gehman, Jr. et al.
patent: 5510653 (1996-04-01), Fujiki et al.
patent: 5635767 (1997-06-01), Wenzel et al.
patent: 5659201 (1997-08-01), Wollesen
patent: 5686764 (1997-11-01), Fulcher
patent: 5739560 (1998-04-01), Toyoda et al.
patent: 5742075 (1998-04-01), Burns et al.
patent: 5767010 (1998-06-01), Mis et al.
patent: 5780882 (1998-07-01), Sugiura et al.
patent: 5818110 (1998-10-01), Cronin
patent: 5818111 (1998-10-01), Jeng et al.
patent: 5827776 (1998-10-01), Bandyopadhyay et al.
patent: 5827778 (1998-10-01), Yamada
patent: 5834844 (1998-11-01), Akagawa et al.
patent: 5834851 (1998-11-01), Ikeda et al.
patent: 5874779 (1999-02-01), Matsuno
patent: 5900668 (1999-05-01), Wollesen
patent: 5910020 (1999-06-01), Yamada
patent: 5953626 (1999-09-01), Hause et al.
patent: 5969424 (1999-10-01), Matsuki et al.
patent: 6020640 (2000-02-01), Efland et al.
patent: 6033939 (2000-03-01), Agarwala et al.
patent: 6046502 (2000-04-01), Matsuno
patent: 6046503 (2000-04-01), Weigand et al.
patent: 6100548 (2000-08-01), Nguyen et al.
patent: 6124912 (2000-09-01), Moore
patent: 6130457 (2000-10-01), Yu et al.
patent: 6144100 (2000-11-01), Shen et al.
patent: 6150726 (2000-11-01), Feilchenfeld et al.
patent: 6184143 (2001-02-01), Ohashi et al.
patent: 6229221 (2001-05-01), Kloen et al.
patent: 6303977 (2001-10-01), Schroen et al.
patent: 6324048 (2001-11-01), Liu
patent: 6472745 (2002-10-01), Iizuka
patent: 6707159 (2004-03-01), Kumamoto et al.
patent: 01-135043 (1989-05-01), None
patent: 01-183836 (1989-07-01), None
patent: 01-184848 (1989-07-01), None
patent: 01-184849 (1989-07-01), None
patent: 04-316351 (1992-11-01), None
Stanley Wolf,Silicon Processing for the VLSI Era vol. 2: Process Integration, Lattice Press, Sunset Beach, CA pp. 214-285, copyright 1990.
Ackerman Stephen B.
Pike Rosemary L.S.
Saile Ackerman LLC
Soward Ida M.
LandOfFree
Top layers of metal for high performance IC's does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Top layers of metal for high performance IC's, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Top layers of metal for high performance IC's will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3868409