Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2007-11-13
2007-11-13
Soward, Ida M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S207000, C257S208000, C257S209000, C257S700000, C257S758000, C257S759000, C257S760000
Reexamination Certificate
active
11121477
ABSTRACT:
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
REFERENCES:
patent: 4423547 (1984-01-01), Farrar et al.
patent: 4618878 (1986-10-01), Aoyama et al.
patent: 4988514 (1991-01-01), Fukuyama et al.
patent: 5055907 (1991-10-01), Jacobs
patent: 5083187 (1992-01-01), Lamson et al.
patent: 5106461 (1992-04-01), Volfson et al.
patent: 5212403 (1993-05-01), Nakanishi et al.
patent: 5384488 (1995-01-01), Golshan et al.
patent: 5468984 (1995-11-01), Efland et al.
patent: 5478781 (1995-12-01), Bertin et al.
patent: 5501006 (1996-03-01), Gehman, Jr. et al.
patent: 5635767 (1997-06-01), Wenzel et al.
patent: 5659201 (1997-08-01), Wollesen
patent: 5686764 (1997-11-01), Fulcher
patent: 5760429 (1998-06-01), Yano et al.
patent: 5767546 (1998-06-01), Williams et al.
patent: 5818110 (1998-10-01), Cronin
patent: 5827776 (1998-10-01), Bandyopadhyay et al.
patent: 5827778 (1998-10-01), Yamada
patent: 5834844 (1998-11-01), Akagawa et al.
patent: 5874770 (1999-02-01), Saia et al.
patent: 5894170 (1999-04-01), Ishikawa
patent: 5910020 (1999-06-01), Yamada
patent: 5953626 (1999-09-01), Hause et al.
patent: 5969424 (1999-10-01), Matsuki et al.
patent: 6020640 (2000-02-01), Efland et al.
patent: 6031257 (2000-02-01), Noto et al.
patent: 6100548 (2000-08-01), Nguyen et al.
patent: 6107674 (2000-08-01), Zommer
patent: 6130457 (2000-10-01), Yu et al.
patent: 6133582 (2000-10-01), Osann et al.
patent: 6136212 (2000-10-01), Mastrangelo et al.
patent: 6144100 (2000-11-01), Shen et al.
patent: 6160297 (2000-12-01), Shimizu et al.
patent: 6169019 (2001-01-01), Takagi
patent: 6175156 (2001-01-01), Mametani et al.
patent: 6184143 (2001-02-01), Ohashi et al.
patent: 6229221 (2001-05-01), Kloen et al.
patent: 6380626 (2002-04-01), Jiang
patent: 6395454 (2002-05-01), Piscevic
patent: 6472745 (2002-10-01), Iizuka
patent: 6707159 (2004-03-01), Kumamoto et al.
patent: 01-135043 (1989-05-01), None
patent: 01-183836 (1989-07-01), None
patent: 01-184848 (1989-07-01), None
patent: 01-184849 (1989-07-01), None
patent: 04-316351 (1992-11-01), None
Stanley Wolf,Silicon Processing for the VLSI Eravol. 2:Process Integration, Lattice Press, Sunset Beach, CA pp. 214-285, copyright 1990.
Ackerman Stephen B.
Lin Mou-Shiung
Pike Rosemary L. S.
Saile Ackerman LLC
Soward Ida M.
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