Top contact alignment in semiconductor devices

Details Top contact alignment in semiconductor devices Top contact alignment in semiconductor devices

2007-01-03

2009-02-24

Lee, Hsien-ming (Department: 2823)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S692000, C438S975000, C257S797000, C257SE23179

Reexamination Certificate

active

07494825

ABSTRACT:
According to an example embodiment, a semiconductor device includes a lower electrode (316) disposed on an oxide layer (302), an upper electrode (320) disposed on the lower electrode, a dielectric pattern (322) disposed on the oxide layer and surrounding the upper electrode, the upper electrode protruding above an upper surface of the dielectric pattern, and a contact pattern (328) that is contiguous with the upper electrode and the dielectric pattern.

REFERENCES:
patent: 6046758 (2000-04-01), Brown et al.
patent: 2003/0186552 (2003-10-01), Amano et al.
patent: 2004/0018645 (2004-01-01), Drewes
patent: 2004/0266188 (2004-12-01), Kondo et al.
patent: 2005/0141148 (2005-06-01), Aikawa et al.
patent: 2006/0060908 (2006-03-01), Mikawa et al.
patent: 2007/0215911 (2007-09-01), Torng et al.

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