Tolerable synchronization circuit of RDS receiver

Details Tolerable synchronization circuit of RDS receiver Tolerable synchronization circuit of RDS receiver

2011-03-15

2011-03-15

Wang, Ted M (Department: 2611)

Pulse or digital communications

Receivers

C375S324000, C375S326000, C375S340000

Reexamination Certificate

active

07907680

ABSTRACT:
A Radio Data System (RDS) decoder circuit determines a subcarrier frequency utilizing only a 57 kHz RDS signal of an FM broadcast signal. The RDS decoder includes a zero-intermediate frequency (zero-IF) FM demodulator, a first mixer, a low-pass filter (LPF) unit, a shaping filter unit, a carrier recovery circuit, a digitally controlled oscillator (DCO), a symbol timing recovery circuit, an integrate and dump circuit, a slicer280, and a differential decoder. The carrier recovery circuit includes a phase error detector and a digital loop filter (DLF). The symbol timing recovery circuit includes a zero-crossing detector, a phase detector and loop filter unit, and a counter.

REFERENCES:
patent: 5507024 (1996-04-01), Richards, Jr.
patent: 6868129 (2005-03-01), Li et al.
patent: 2007/0047737 (2007-03-01), Lerner et al.

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