TOI and power compression bias network

Amplifiers – With semiconductor amplifying device – Including particular biasing arrangement

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C330S288000

Reexamination Certificate

active

06529080

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing active bias networks generally and, more particularly, an active bias network configured to increase Third-Order Intercept, the 1 dB (decibel) compression point, and improve noise performance of an integrated circuit (IC) amplifier. The present invention may also provide a simplified method of packaging.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a typical amplifier
10
that may be used for biasing is shown. The amplifier
10
implements a resistor string RA and RB for biasing. The resistor string RA and RB provides a correct base (or gate voltage) for a desired device current. However, the resistor string (or divider) RA and RB does not provide temperature or process variation correction.
Referring to
FIG. 2
, a typical biased amplifier circuit is shown. The amplifier
20
includes a bias network of a number of resistors R
1
, R
2
, R
3
, R
4
, and R
5
, a transistor Q
1
, a transistor Q
2
and a capacitor C
1
. The amplifier
20
includes the bias network to provide temperature and process variation correction. However, the bias network does not correct for the non-linearity of the network.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising an amplifier and a circuit. The amplifier may be configured to amplify an input signal. The circuit may be configured to (i) control the amplifier, (ii) compensate for non-linear characteristics of the amplifier and (iii) increase the third-order intercept (TOI).
The objects, features and advantages of the present invention include providing a method and/or architecture for active bias networks that may (i) improve the third-order intercept (TOI) (ii) improve noise performance of an integrated circuit amplifier, (iii) improve the 1 dB compression point without the use of external components, (iv) implement a three terminal integrated circuit and/or (v) be implemented in a low cost package.


REFERENCES:
patent: 5517688 (1996-05-01), Fajen et al.
patent: 5590411 (1996-12-01), Sroka et al.
patent: 5678226 (1997-10-01), Li et al.
patent: 5710523 (1998-01-01), Kobayashi
patent: 6275687 (2001-08-01), Lloyd
“An HBT MMIC Power Amplifier with an Integrated Diode Linearizer for Low-Voltage Portable Phone Applications”, By: Toshihiko Yoshimasu et al., IEEE Journal of Solid-State Circuits, vol. 33, No. 9, Sep. 1998, pp. 1290-1296.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

TOI and power compression bias network does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with TOI and power compression bias network, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and TOI and power compression bias network will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3054900

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.