Toggle-free scan flip-flop

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307442, H03K 3284, H03K 19007

Patent

active

050158759

ABSTRACT:
A toggle-free scan flip-flop (TFSFF) is provided which is designed for use during a test mode scan operation. The toggle-free scan flip-flop has the capability of not toggling its parallel output during test mode scan operation. The TFSFF uses a master latch, which is controlled by a scan multiplexor, to selectively update two alternate slave latches. Switching logic controls the determination of which alternate slave latch is updated with the incoming data signal. An existent scan enable (SE) signal controls the switching logic, and thus, the TFSFF design requires no additional control signals for its operation. During the scan test mode, the data is clocked through the TFSFF from a Scan-Data-In terminal, and out the Scan-Data-Out terminal, without affecting the system data output Q. The shift sequence is followed by a capture interval, during which the Q output is automatically updated with the desired data to test the target logic. Thus, the logic under test is not affected by the loading of the scan test vector, since the parallel system output Q of the TFSFF does not toggle during the shifting sequence.

REFERENCES:
patent: 4495629 (1985-01-01), Zasio et al.
patent: 4879718 (1989-11-01), Sanner
"An Enhancement to LSSD and Some Applications of LSSD in Reliability, Availability, and Serviceability", DasGupta et al., The Eleventh Annual International Symposium on Fault-Tolerant Computing, Jun. 24-26, 1981, pp. 32-34.

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