Toggle flip-flop network with a reduced integration area

Details Toggle flip-flop network with a reduced integration area Toggle flip-flop network with a reduced integration area

1998-08-28

2000-05-30

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327216, 327217, H03K 3037

Patent

active

060695137

ABSTRACT:
A toggle flip-flop with reduced integration area, comprising a flip-flop of the D-type with an inverting input stage and a master-slave portion. Three transistors connected to the inverting stage form a logic gate of the XOR type whereto the output terminal of the master-slave portion is fed back.

REFERENCES:
patent: 3755692 (1973-08-01), Mundy
patent: 4233524 (1980-11-01), Burdick
patent: 5306970 (1994-04-01), Phillips
patent: 5334888 (1994-08-01), Bodas
patent: 5923185 (1999-07-01), Zhou
patent: 5952850 (1999-09-01), Hojo et al.

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