Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Reexamination Certificate
1997-05-30
2003-05-06
Talbot, Brian K. (Department: 1762)
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
C427S123000, C427S377000, C427S383100, C438S627000, C438S643000, C438S653000, C438S655000, C438S660000, C438S681000
Reexamination Certificate
active
06558739
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to barrier layers within integrated circuits. More particularly, the present invention relates to composite barrier layers within integrated circuits.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
In the process of forming within integrated circuits patterned conductor layers for connecting and interconnecting electrical circuit elements formed within and upon semiconductor substrates, it is common in the art to employ a barrier layer formed interposed between an electrode contact of an electrical circuit element and a conductor layer, typically an aluminum containing conductor layer, desired to be formed contacting the electrode contact of the electrical circuit element. Such barrier layers provide a barrier to: (
1
) inhomogeneous inter-diffusion of the electrode contact with the conductor layer; and/or (
2
) spiking of the conductor layer (when the conductor layer is formed from an aluminum containing conductor material) into the electrode contact. When an electrode contact is formed from a silicon containing material to yield a silicon containing electrode contact, as is most common in the art, there is typically also employed a metal silicide layer formed upon the electrode contact, typically through annealing a metal silicide forming metal layer in contact with the silicon containing electrode contact, in order to provide a low resistance connection to the electrical circuit element.
A typical electrical circuit element electrode contact employing such a barrier layer and a metal silicide layer (formed from a metal silicide forming metal layer) is illustrated by the schematic cross-sectional diagram of FIG.
1
. Shown in
FIG. 1
is a silicon semiconductor substrate
10
having formed upon its surface a pair of patterned dielectric layers
12
a
and
12
b
which define a window accessing the silicon semiconductor substrate
10
. Formed through partial consumption of a blanket metal silicide forming metal layer (not shown) formed in contact with the portion of the silicon semiconductor substrate
10
exposed within the window is a metal silicide layer
14
, along with a pair of metal silicide forming metal layer residues
16
a
and
16
b
. There is also shown formed upon the metal silicide forming metal layer residues
16
a
and
16
b
, and the metal silicide layer
14
, a blanket barrier layer
18
. Finally, there is shown in
FIG. 1
a blanket conductor layer
20
formed upon the blanket barrier layer
18
, where the blanket conductor layer
20
has formed thereupon a patterned photoresist layer
21
. Within the electrical circuit element electrode contact structure whose schematic cross-sectional diagram is illustrated in
FIG. 1
, the metal silicide layer
14
is typically, although not exclusively, a titanium silicide layer, while the metal silicide forming metal layer residues
16
a
and
16
b
are thus typically, although not exclusively, titanium metal layer residues. In addition, the blanket barrier layer
18
is typically a blanket titanium-tungsten alloy barrier layer since titanium-tungsten alloy barrier layers typically have superior step coverage within narrow high aspect ratio apertures. Further, as is most common in the art, the blanket conductor layer
20
is typically a blanket aluminum containing conductor layer. Finally, the patterned photoresist layer
21
is formed of a photoresist material which is susceptible to stripping within a photoresist stripping/polymer removal composition which employs a hydroxyl/amine compound such as but not limited to hydroxylamine (ie: NH
2
OH; (HDA)) and bis (2-aminoethoxy)-2-ethanol (ie: (NH
2
CH
2
CH
2
O)
2
CHCH
2
OH; (DGA)).
While the electrical circuit element electrode contact structure whose schematic cross-sectional diagram is illustrated in
FIG. 1
has become quite common in the art of integrated circuit fabrication, the electrical circuit element electrode contact structure whose schematic cross-sectional diagram is illustrated in
FIG. 1
is not entirely without problems. In particular, when patterning the electrical circuit element electrode contact structure whose schematic cross-sectional diagram is illustrated in
FIG. 1
to form a patterned electrical circuit element electrode contact structure there is often observed partial delamination of a patterned barrier layer from the patterned dielectric layers
12
a
and
12
b
when the metal silicide forming metal layer residues
16
a
and
16
b
are formed of titanium. A schematic cross-sectional diagram illustrating the mechanism through which such partial delamination occurs is illustrated in FIG.
2
.
Shown in
FIG. 2
is a patterned conductor layer
20
′ formed upon a patterned barrier layer
18
′, where the patterned conductor layer
20
′ is patterned from the blanket conductor layer
20
and the patterned barrier layer
18
′ is successively patterned from the blanket barrier layer
18
. Also shown in
FIG. 2
is a pair of voids
22
where the patterned barrier layer
18
′ and the patterned conductor layer
20
′ have delaminated from the patterned dielectric layers
12
a
and
12
b
. Such delamination typically occurs due to etching and undercutting of a pair of patterned metal silicide forming metal layer residues formed of titanium (not shown) successively patterned from the metal silicide forming metal layer residues
16
a
and
16
b
, where the etching and undercutting occurs due to contact of the patterned metal silicide forming metal layer residues with a stripping composition employed in removing from the surface of the electrode contact structure whose schematic cross-sectional diagram is illustrated in
FIG. 2
a patterned photoresist layer employed in defining the patterned conductor layer
20
′, the patterned barrier layer
18
′ and the patterned metal silicide forming metal layer residues. In particular, when the metal silicide forming metal layer residues
16
a
and
16
b
are formed of titanium, photoresist stripping/polymer removal compositions which employ hydroxyl/amine compounds such as but not limited to hydroxylamine (ie: NH
2
OH; (HDA)) and bis (2-aminoethoxy-2-ethanol) (ie: (N
2
CH
2
CH
2
O)
2
CHCH
2
OH; (DGA)) may be particularly efficient in etching patterned titanium metal silicide forming metal layers residues to provide the undercutting and void
22
formation as illustrated in FIG.
2
.
It is therefore desirable in the art to provide methods for forming electrical circuit element contact structures such that the contact structures are not susceptible to delamination from surfaces of substrates upon which are formed those contact structures, due to etching with stripper solutions of metal silicide forming metal layers formed within those structures, that the present invention is generally directed.
Novel barrier layer constructions which provide improved properties to integrated circuits are know within the art of integrated circuit fabrication. For example, Ngan et al. in U.S. Pat. No. 5,378,660 and U.S. Pat. No. 5,504,043 disclose a titanium nitride barrier layer construction with improved diffusion barrier properties for aluminum layers formed at elevated temperatures upon the titanium nitride barrier layer construction. The titanium nitride barrier layer within the titanium nitride barrier layer construction has incorporated therein additional oxygen. In addition, Wang et al., in U.S. Pat. No. 5,508,212 disclose a large tilt angle method for forming a titanium nitride layer which limits encroaching of titanium silicide layers within a field effect transistor within an integrated circuit.
Desirable in the art are additiona
Lin Charles
Lin Yih-Shung
Liu Erzhuang
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saile George O.
Talbot Brian K.
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