Timing vernier using a delay locked loop

Details Timing vernier using a delay locked loop Timing vernier using a delay locked loop

2006-05-02

2006-05-02

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Phase shift by less than period of input

C327S244000

Reexamination Certificate

active

07038517

ABSTRACT:
A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse. The difference signal pulse is coupled to the bias input of the verniers to adjust the delay range, such that the duty cycle of the difference signal approaches the duty cycle of the reference pulse signal. In one embodiment there is provided a circuit for implementing the method.

REFERENCES:
patent: 5684421 (1997-11-01), Chapman et al.
patent: 6052011 (2000-04-01), Dasgupta
patent: 6121826 (2000-09-01), Dosho et al.
patent: 6680635 (2004-01-01), Lee
patent: 6774694 (2004-08-01), Stern et al.

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