Timing vernier architecture for generating high speed, high...

Details Timing vernier architecture for generating high speed, high... Timing vernier architecture for generating high speed, high...

2002-12-24

2004-08-10

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S284000, C327S294000

Reexamination Certificate

active

06774694

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to timing verniers, and more particularly to the generation of high speed, high accuracy timing edges.
2. Description of the Related Art
The automatic test equipment (ATE) industry, among others, requires the generation of high speed pulse edges with controllable delays between successive edges. For a variety of cost and integration reasons, CMOS circuitry is preferred. Timing verniers have been constructed using delay cells with delays sensitive to some bias level, with that level stabilized across processing and environmental variations by the use of a feedback loop, either a delay-lock-loop or a phase-lock-loop, and a time reference, usually the period of an input digital clock. Due to the overhead involved in such systems, it is not practical to provide separate loops to generate more than a few independent bias levels.
The desired delays are determined by a data stream of digital input signals. Timing verniers typically consist of controllable delay cells, delay control circuitry, delay calibration circuitry and functional control circuitry. The demands of fast refire (the ability to generate multiple pulse edges rapidly) and high accuracy are difficult to achieve simultaneously.
SUMMARY OF THE INVENTION
A timing vernier which provides substantially glitchless operation, minimizes the effect of previous timing reference signals on the timing accuracy for the present signal, allows for fast refire, and enables the production of finely tuned timing signals with low mismatch errors is provided. Particular embodiments of the invention employ coarse and fine multiplexers to establish the vernier output, with stable bias levels applied to intermediate points of an impedance string to establish reliable bias levels for delay cells associated with the fine multiplexer. The bias levels can be established by delay-lock-loops that are also employed to establish timing reference signal trains for the coarse multiplexer.
The vernier is permitted to output a new timing reference signal only if that signal lags the preceding output signal by at least one clock period. The coarse multiplexer switches to the next timing reference signal train substantially immediately upon processing a preceding valid signal, thus maximizing the time available for the system to settle before the next timing reference edge. Multiple control regimes are provided for different phase differentials between succeeding timing reference signals, ensuring that invalid outputs are suppressed regardless of the state of the next timing reference at the instant of switching. Look-ahead logic allows the phase comparisons to be made in advance of reading out the timing commands.
A hold off capability is also provided that prevents the production of an output signal when such prevention is desired by the user, and is distinguished from validating mask timing commands inserted to satisfy the minimum phase lag requirement. The look-ahead logic is also used to jump over the validating mask commands in the command data store to keep the average read out rate synchronized with the command write rate.
These and further objects and features of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.


REFERENCES:
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patent: 6100735 (2000-08-01), Lu
patent: 6580304 (2003-06-01), Rieven

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