Timing verification checking value extracting method

Details Timing verification checking value extracting method Timing verification checking value extracting method

2000-11-07

2004-09-07

Paladini, Albert W. (Department: 2125)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Timing

C703S013000, C327S155000

Reexamination Certificate

active

06789055

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a timing verification checking value extracting method used for the timing verification of pulses of a semiconductor integrated circuit.
2. Description of Related Art
In a design stage of a semiconductor integrated circuit, one or more input pulses are respectively input to a designed cell as a simulation, and it is checked whether or not one or more output pulses respectively reach an expected value within a prescribed time in response to the input pulses. Therefore, it is verified whether the input timing of the input pulses input to the designed cell is good or bad.
FIG. 17
is a flow chart showing a conventional timing verification checking value extracting method. As a prior art, a set up value is extracted as a timing verification checking value according to this conventional timing verification checking value extracting method of FIG.
17
. For example, in case of the timing verification of pulses of a D type flip-flop circuit
11
shown in
FIG. 3
, the set up value denotes a time period required for the setting up of a data pulse
15
before the level change of a clock pulse
16
so as to prevent an erroneous operation of the D type flip-flop circuit
11
.
As shown in
FIG. 17
, a waveform table and circuit connection information are prepared in advance (steps ST
1
and ST
2
). In the waveform table, waveforms of both the data pulse
15
and the clock pulse
16
to be input to the D type flip-flop circuit
11
, an initial setting value of a pulse
5
time difference
18
between the data pulse
15
and the clock pulse
16
, an initial changing degree of the pulse time difference
18
, a simulation completion time and a convergence condition of the pulse time difference
18
are written. Also, the circuit connection information indicates the arrangement of a plurality of transistors, resistors and capacitors composing the D type flip-flop circuit
11
.
Thereafter, a group of steps
3
,
4
,
5
and
7
corresponding to one simulation stage is repeatedly performed. That is, a data pulse
15
and a clock pulse
16
to be input to the D type flip-flop circuit
11
are produced according to a setting value of the pulse time difference
18
and a changing degree of the pulse time difference
18
in a pulse producing process (step ST
3
). More precisely, in a first simulation stage of the step ST
3
, the data pulse
15
and the clock pulse
16
are produced so as to make the data pulse
15
earlier than the clock pulse
16
by the initial setting value written in the waveform table, and the changing degree of the pulse time difference
18
is set to the initial changing degree written in the waveform table.
Thereafter, in a simulation process (step ST
4
), the data pulse
15
is supplied to a data input terminal
12
of the D type flip-flop circuit
11
, the clock pulse
16
is supplied to a clock input terminal
13
of the D type flip-flop circuit
11
at the pulse time difference
18
from the data pulse
15
, a level of an output pulse
17
output from an output terminal
14
of the D type flip-flop circuit
11
is checked at the simulation completion time written in the waveform table, and it is judged whether the level of the output pulse
17
is good or bad.
The judgment of the level of the output pulse
17
is shown with the level changes of the pulses
15
,
16
and
17
in FIG.
5
. As shown in
FIG. 5
, a circuit simulation is started at a simulation start time
21
, and it is judged whether the level of the output pulse
17
(an output pulse
17
a
or an output pulse
17
b
) becomes higher than a reference voltage
23
until the simulation completion time
22
. In cases where the pulse time difference
18
is large, the level of the output pulse
17
a
corresponding to the large pulse time difference
18
becomes higher than the reference voltage
23
until the simulation completion time
22
in response to the inputting of a data pulse
15
a
corresponding to the large pulse time difference
18
and the clock pulse
16
, and it is judged that the level of the output pulse
17
a
is good. This judgment is called an affirmative judgment in this specification. In contrast, in cases where the pulse time difference
18
is small, the level of the output pulse
17
b
corresponding to the small pulse time difference
18
does not become higher than the reference voltage
23
until the simulation completion time
22
in response to the inputting of a data pulse
15
b
corresponding to the small pulse time difference
18
and the clock pulse
16
, and it is judged that the level of the output pulse
17
b
is not good. This judgment is called a negative judgment in this specification. Therefore, in cases where the pulse time difference
18
between the data pulse
15
and the clock pulse
16
is large, it is judged that the input timing of the data pulse
15
satisfies the set up value which denotes a time period required for the setting up of the data pulse
15
before the level change of the clock pulse
16
so as to prevent an erroneous operation of the D type flip-flop circuit
11
(the affirmative judgment). In contrast, in cases where the pulse time difference
18
is small, it is judged that the input timing of the data pulse
15
does not satisfy the set up value (the negative judgment). In the simulation process performed in the first simulation stage, as shown in
FIG. 6
, because the pulse time difference
18
is set to the initial setting value
26
(indicated by a simulation stage number (
1
) in
FIG. 6
) which is sufficiently high, the affirmative judgment is obtained.
After this simulation process (step ST
4
) is performed, it is judged in a convergence judging process (step ST
5
) whether or not a changing degree of the pulse time difference
18
is within a prescribed range. As shown in
FIG. 6
, because a changing degree of the pulse time difference
18
is set to the initial changing degree
27
in the first simulation stage, the changing degree of the pulse time difference
18
is not within the prescribed range. Therefore, the convergence condition is not satisfied. Thereafter, in cases where it is judged in the convergence judging process that the changing degree of the pulse time difference
18
is out of the prescribed range, a pulse time difference resetting process (step ST
7
) is performed. In this process, a setting value of the pulse time difference
18
set in the pulse producing process (step ST
3
) is changed according to the judgment performed in the simulation process (step ST
4
), and a changing degree of the pulse time difference set in the pulse producing process (step ST
3
) is reduced in cases where the affirmative (or negative) judgment of the simulation process obtained in a preceding simulation stage changes to the negative (or affirmative) judgment in a current simulation stage.
More precisely, as shown in
FIG. 6
, in cases where the affirmative judgment of the simulation process is obtained in both the preceding and current simulation stages, the setting value of the pulse time difference
18
is decreased by the changing degree of the pulse time difference
18
, and the changing degree of the pulse time difference
18
is maintained. Also, in cases where the affirmative judgment of the simulation process obtained in the preceding simulation stage changes to the negative judgment in the current simulation stage, because a set up truth value
29
to be idealistically extracted exists between a pulse time difference in the preceding simulation stage and a pulse time difference in the current simulation stage, the changing degree of the pulse time difference
18
is halved, and the setting value of the pulse time difference
18
is increased by the halved changing degree. Also, in cases where the negative judgment of the simulation process obtained in the preceding simulation stage changes to the affirmative judgment in the current simulation stage, because the set up truth value
29
exists between pulse time differences of the preceding and cu

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