Timing synchronization methods and systems for transmit...

Pulse or digital communications – Synchronizers

Reexamination Certificate

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Details

C327S141000, C370S503000, C709S248000

Reexamination Certificate

active

06977980

ABSTRACT:
Transmit parallel interfaces and methods are provided in which a clock signal is generated that maximizes the setup and hold window of input data. In at least some embodiments, a divider circuit provides a clock signal in one clock domain that has a rising edge located very close to the falling edge of a system clock in another clock domain.

REFERENCES:
patent: 3646517 (1972-02-01), Waters et al.
patent: 4461013 (1984-07-01), Lese et al.
patent: 4727541 (1988-02-01), Mori et al.
patent: 4965797 (1990-10-01), Yamane et al.
patent: 6009107 (1999-12-01), Arvidsson et al.
patent: 6335696 (2002-01-01), Aoyagi et al.
patent: 6430242 (2002-08-01), Buchanan et al.
patent: 2002/0085655 (2002-07-01), Johnson
patent: 2002/0091885 (2002-07-01), Hendrickson et al.

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