Timing synchronization circuit

Details Timing synchronization circuit Timing synchronization circuit

1983-07-29

1986-06-17

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

370 85, 370100, H04L 700

Patent

active

045960259

ABSTRACT:
A timing synchronization circuit for use in a multi-station communication system in which one station is a master station. The timing synchronization circuit within each station comprises a clock operating at a frequency nearly constant between the stations. The clock signal is frequency-divided to provide synchronization of the frames and blocks of the data being transmitted. The clock signal is reinitialized by a reset signal generated when a packet of data transmitted by the master station is received and recognized by the station by identifying code within the packet. The reinitialization accounts for the propagation delays relative to the master station.

REFERENCES:
patent: 3641274 (1972-02-01), Sasaki et al.
patent: 3772475 (1973-11-01), Loffreda
patent: 3813496 (1974-05-01), Maillet
patent: 3825899 (1974-07-01), Haeberle et al.
patent: 3922496 (1975-11-01), Gabbard et al.
patent: 3958083 (1976-05-01), Hara et al.
patent: 4017684 (1977-04-01), Kurihara et al.
patent: 4054753 (1977-10-01), Kaul et al.
patent: 4271505 (1981-06-01), Menot et al.

Affiliated with

Also associated with

Rating

Timing synchronization circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Timing synchronization circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing synchronization circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2276785