Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-09-06
2004-07-27
Nguyen, Linh M. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S161000
Reexamination Certificate
active
06768360
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a timing signal generation circuit arranged to generate timing signals of high resolution suitable for use in electrical devices such as an IC test system.
2. Description of the Related Art
An example of conventional timing signal generation circuits is shown in Japanese Patent Laid-open No. H5(1993)-136664.
The timing signal generation circuit of the document will be explained with reference to
FIG. 6
as a first conventional example.
FIG. 6
is a circuit diagram illustrating the structure of the first conventional timing signal generation circuit.
As shown in
FIG. 6
, this timing signal generation circuit is provided with a CMOS constructed of a p-channel FET
201
and an n-channel FET
202
. The gate of the COMS is connected to an input terminal
208
, while the drain thereof is connected to an output terminal
207
. The source of the FET
202
is connected to a negative power supply terminal
205
through resister elements
204
constructed of n-channel switchable FETs whose resistance is respectively R
0
, R
1
, R
2
, . . . and the source of the FET
201
is connected to a positive power supply terminal
205
through resister elements
203
constructed of n-channel switchable FETs whose resistance is respectively R
0
, R
1
, R
2
, . . .
Since a plurality of pairs of resistor elements are provided in one delay circuit, many delay amounts can be set. If this circuit is used as one stage of multistage delay circuit, a great number of delay amounts can be set with a few delay stages. Consequently, delay amounts of high resolution can be obtained with a small dispersion.
Another example of conventional timing signal generation circuits is shown in Japanese Patent Laid-open No. H8(1996)-51346 and U.S. Pat. No. 5,491,673.
The timing signal generation circuit of these documents will be explained with reference to
FIG. 7
as a second conventional example.
FIG. 7
is a circuit diagram illustrating the structure of the second conventional timing signal generation circuit.
As shown in
FIG. 7
, this timing signal generation circuit is constructed of a variable delay circuit
120
, a phase comparator
140
, a feedback circuit
150
, a synchronous delay circuit
110
and a selector circuit
130
.
The variable delay circuit
120
is constructed of m-stage variable delay elements
52
1
, to
52
m
(“m” is an integer of 2 or more) which are serially connected each other. Each of the variable delay elements generates a minute delay which is 1/m of a clock period.
The phase comparator
140
compares the phase of a delay amount of all the variable delay elements or an output (e
1
) of the final variable delay element
52
m
with the phase of a clock signal (e
2
) to produce a phase difference as a voltage signal.
The feedback circuit
150
feeds back the voltage signal supplied from the phase comparator
140
to each of the variable delay elements. This feedback allows the maintenance of a phase lock state where a delay amount of all the variable delay elements coincides with a clock period. The variable delay circuit
120
, the phase comparator
140
and the feedback circuit
150
constitute a phase synchronous loop circuit unit
100
.
The synchronous delay circuit
110
generates an output signal of a delay time which is an integer multiple of a clock period based on upper digitals of delay data (delay code).
The selector circuit
130
has AND gates
54
1
to
54
m
provided one for each of the variable delay elements
52
1
to
52
m
. An output of a variable delay element, a selection signal “s” generated by a decoder
160
based on lower digitals of delay data (delay code), and an output of the synchronous delay circuit
110
are supplied to the corresponding AND gate. Selection signals “s” are generated corresponding to bits, respectively. An output of each AND gate
54
1
to
54
m
is supplied to an OR gate
58
. The OR gate
58
then generates and outputs a timing signal.
The selector circuit
130
outputs a timing signal by selecting a minute delay from any one of the variable delay elements
52
of the variable delay circuit
120
on the basis of selection signals generated by the decoder
160
.
In this conventional timing signal generation circuit, changes in delay amount are prevented by a negative feedback loop of the phase synchronous loop circuit unit
100
, thereby preventing decreases in timing accuracy. Thus, the timing signal generation circuit can generate timing signals with high accuracy, even when an IC, e.g. composed of a CMOS, which controls the power supply voltage of the variable delay elements
52
1
to
52
m
and the like is adversely affected by disturbances such as changes in temperature or power supply voltage.
Further, in this timing signal generation circuit, each of the variable delay elements
52
1
to
52
m
of the variable delay circuit
120
always operates in synchronism with highly accurate clock signals. As a result, the amount of self-generating heat of the variable delay circuit
120
is stable without any time variation. Thus, the negative feedback loop of the phase synchronous loop circuit unit
100
is required only to respond to disturbances, not to have the high-speed response capability.
If necessary, a delay amount of a timing signal against a clock signal may be changed. In such a situation, the delay amount is required to be changed with high resolution, the delay amount is required to be changed with high resolution, e.g., as high as several picoseconds in operation of the timing signal generation circuit.
However, in the timing signal generation circuit of Japanese Patent Laid-open No. H5(1993)-136664, if a delay amount changes in operation (hereinafter referred to as “on-the-fly”), a phase difference comparator disadvantageously detects a phase change caused by this change. If a variable delay element receives, as a feedback signal, the change corresponding to the on-the-fly, which is contained in a voltage signal output from the phase difference comparator, the phase lock may be released, resulting in a timing error.
In the timing signal generation circuit of Japanese Patent Laid-open No. H8(1996)-51346 and U.S. Pat. No. 5,491,673, since a delay amount of each variable delay element
52
is at least the amount of single-stage gate, the resolution of a variable delay amount is as low as several hundreds picoseconds. In other words, high resolution, e.g., as high as several picoseconds, cannot be obtained. Thus, further technical improvement is required for the conventional timing signal generation circuits.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a timing signal generation circuit where a delay amount can be changed in operation with high resolution, while maintaining a phase lock state.
According to a first aspect of the present invention, there is provided a timing signal generation circuit comprising: a negative feedback loop for maintaining a phase lock state; the negative feedback loop comprising; a variable delay circuit for outputting a timing signal delayed from an input clock signal by a delay amount designated by a delay code; a phase difference detector for detecting a phase difference between the timing signal and the input clock signal to output a detection signal; and a loop filter for smoothing a waveform of the detection signal to generate a voltage signal and for feeding the voltage signal back to the variable delay circuit: and a cancel unit for generating a reverse detection signal based on the delay code to cancel the phase difference caused by a change in the delay amount where the reverse detection signal is supplied to the low pass filter.
In this timing signal generation circuit, the cancel unit generates a reverse detection signal for canceling a detection signal due to the on-the-fly change of the delay code, while the negative feedback loop presents the occurrence of a timing error caused by disturbances and the like. As a result, in this negative feedback loop, a voltage s
Advantest Corp.
Muramatsu & Associates
Nguyen Linh M.
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