Timing signal generating circuit

Details Timing signal generating circuit Timing signal generating circuit

2000-04-06

2003-07-29

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S109000, C327S153000, C327S158000, C331SDIG002, C375S376000

Reexamination Certificate

active

06600352

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a timing signal generating circuit and a variable delay circuit, and more particularly, to a timing signal generating circuit and a variable delay circuit employed in a delay locked loop circuit of a semiconductor memory device.
An LSI device, such as a synchronous DRAM (SDRAM), includes a delay locked loop (DLL) circuit or a phase locked loop (PLL) circuit to generate an internal clock signal. The internal clock signal is generated based on an external clock signal of an external device and used to control the data input timing or data output timing of an internal circuit.
The delay circuit generates the internal clock signal such that it is synchronized with or delayed from an external clock signal in correspondence with changes in the characteristics of the output terminal of the SDRAM. A stub series termination logic (SSTL) interface, which is suitable for high speed processing, is employed as the input/output terminal of the SDRAM. Since the amplitude of the signal generated by the SSTL interface is relatively small, high timing accuracy is required. Jitter of the internal clock signal must be minimized to achieve the timing accuracy. That is, in a DLL circuit, differences in the delay amount of delay elements, which are used to delay the external clock signal, and deviations between a pseudo I/O interface signal generated in the device and an external I/O interface signal must be minimized.
FIG. 1
is a schematic block diagram showing an SDRAM
50
. The SDRAM
50
has a memory circuit
51
, which includes a data output buffer
52
and a memory circuit block
51
a,
and a DLL circuit
60
. The DLL circuit
60
generates an internal clock signal used to control the output timing of data.
The memory circuit block
51
a
receives various signals, such as an external clock signal CLK, an external command signal, an address signal, and write data. Based on the external command signal, the memory circuit block
51
a
performs various processes, such as writing or reading data.
The data output buffer
52
transmits read data RD from the memory circuit block
51
a,
in accordance with the internal clock signal CK from the DLL circuit
60
, to an external input device
54
via an external output terminal
53
of the SDRAM
50
and an SSTL interface
56
. The SSTL interface
56
performs level conversion on the theoretical amplitude of the read data RD and generates an external I/O interface signal DQ. The external I/O interface signal DQ is sent to the external input device
54
.
FIG. 2
is a circuit diagram showing the data output buffer
52
and the SSTL interface
56
. The data output buffer
52
includes a pull-up p-channel (PMOS) transistor Q
1
and a pull-down n-channel MOS (NMOS) transistor Q
2
, which are connected in series between a high potential power supply VDD and a low potential power supply VSS. The read data RD is applied to the gates of the PMOS transistor Q
1
and the NMOS transistor Q
2
via a transfer gate (not shown), which opens in response to the rising of the internal clock signal CK. The read data RD is output from a node between the PMOS transistor Q
1
and the NMOS transistor Q
2
and provided to the SSTL interface
56
via the external output terminal
53
.
The SSTL interface
56
includes a resistor R
1
connected to the external output terminal
53
, a pull-up resistor R
2
connected to the resistor RI, and a pull-up resistor R
3
connected to an external input terminal
55
of the external input device
54
. A final voltage VTT is applied to the pull-up resistors R
2
, R
3
. A line L is connected to a node between the resistor R
1
and the pull-up resistor R
2
and a node between the pull-up resistor R
3
and the external input terminal
55
. The resistor R
1
is preferably 25 ohms and the resistors R
2
, R
3
are preferably 50 ohms.
The SSTL interface
56
generates the external I/O interface signal DQ (FIG.
8
), which amplitude is smaller than the theoretical amplitude of the read data RD, and sends the external I/O interface signal DQ to the external input terminal
55
. An input buffer
54
a
of the external input device
54
compares the external I/O interface signal DQ to a reference signal VREF and generates a waveform-shaped external I/O interface signal.
As shown in
FIG. 1
, the DLL circuit
60
includes a clock input buffer
61
, a delay circuit section
62
, a pseudo interface circuit section
63
, a pseudo signal input buffer
64
, a determination circuit section
65
, and a delay control circuit section
66
.
The clock input buffer
61
receives the external clock signal CLK from an external device (not shown) and compares the clock signal CLK with the reference signal VREF to generate a waveform-shaped external clock signal WCLK. The clock input buffer
61
causes the waveform-shaped external clock signal WCLK to go high when the external clock signal CLK becomes equal to or higher than the reference signal VREF and causes the waveform-shaped external clock signal WCLK to go low when the external clock signal CLK becomes lower than the reference signal VREF.
The delay circuit section
62
receives the waveform-shaped external clock signal WCLK and delays it for a predetermined time in accordance with a control signal from the delay control circuit section
66
to generate the internal clock signal CK.
FIG. 6
is a circuit diagram showing the delay circuit section
62
, which has a plurality (an n number) of delay circuits DM
1
-DMn that are connected in series. A high potential power supply VDD and a low potential power supply VSS are applied to each of the delay circuits DM
1
-DMn via power supply lines Lp, Ln.
The first delay circuit DM
1
receives the waveform-shaped external clock signal WCLK from the clock input buffer
61
and sends a delayed clock signal to the next delay circuit DM
2
and so on. In this manner, the waveform-shaped external clock signal WCLK is sequentially delayed as it is passed on to the subsequent delay circuits. Thus, the delay between the external clock signal CLK and the delayed clock signal increases at each delay circuit DMn.
The output terminal of each of the delay circuits DM
1
-DMn is connected to an internal clock signal output line L
2
via gate transistors GT
1
-GTn, which are preferably NMOS transistors. Selection signals SL
1
-SLn are received from the delay control circuit section
66
to activate a selected one of the gate transistors GT
1
-GTn. The delayed clock signal output by the delay circuit DMn corresponding to the activated gate transistor is provided to the internal clock signal output line L
2
. In other words, the delay circuit DMn selected by the delay control circuit section
66
provides the internal clock signal output line L
2
with a delayed clock signal that is delayed by a predetermined time. In this manner, a phase controlled internal clock signal CK is generated. The delayed (phase controlled) internal clock signal CK is sent to the data output buffer
52
and the pseudo interface circuit section
63
.
The pseudo interface circuit section
63
receives the internal clock signal CK from the delay circuit section
62
, converts the level of the internal clock signal CK, and generates a pseudo I/O interface signal dDQ that is an approximation of the external I/O interface signal DQ provided to the external input device
54
. In other words, the pseudo interface circuit section
63
has a transmission characteristic that approximates the transmission characteristic of the SSTL interface
56
.
FIG. 4
is a circuit diagram showing the conventional pseudo interface circuit section
63
, which includes an output portion
63
a
and an interface portion
63
b.
The output portion
63
a
has a pull-up PMOS transistor Q
11
and a pull-down NMOS transistor Q
12
connected in series between the high potential power supply VDD and the low potential power supply VSS. The internal clock signal CK is provided to the gate of the PMOS transistor Q
11
and the gate of the NMOS transistor Q
12
.
The circuit configuration of the int

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