Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Patent
1997-04-17
2000-05-02
Chow, Dennis-Doon
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
345100, 345 93, 349 54, 326 11, G09G 336
Patent
active
060578238
ABSTRACT:
A timing signal generating circuit has a plurality of timing signal generating units disposed in series, each including three or more pieces of timing signal generating elements connected in parallel, and a connecting unit disposed in between the plurality of timing signal generating units. The connecting unit includes an arithmetic circuit which outputs relatively majority signal among outputs of the timing signal generating elements.
In this circuit, if some of the timing signal generating elements output defective signals, normal signal is picked-up and output through majority operation of the arithmetic circuit without repairing.
REFERENCES:
patent: 5140594 (1992-08-01), Haulin
patent: 5537583 (1996-07-01), Truong
patent: 5559459 (1996-09-01), Back et al.
patent: 5680408 (1997-10-01), Tsirkel
patent: 5784386 (1998-07-01), Norris
patent: 5859627 (1999-01-01), Hoshiya et al.
Aoki Yoshiro
Miyatake Masaki
Awad Amr
Chow Dennis-Doon
Kabushiki Kaisha Toshiba
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