Horology: time measuring systems or devices – Time interval – Electrical or electromechanical
Reexamination Certificate
1999-06-28
2001-05-01
Miska, Vit (Department: 2859)
Horology: time measuring systems or devices
Time interval
Electrical or electromechanical
C327S175000, C327S263000, C327S291000
Reexamination Certificate
active
06226230
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a timing signal generating apparatus for generating a timing signal on the basis of a program, a method of detecting any set error to the program for a timing signal, and a semiconductor device testing apparatus using such timing signal generating apparatus. More particularly, the present invention relates to a timing signal generating apparatus provided with a set error detecting means being capable of immediately detecting any description error that may exist in a preset program, a method of detecting any set error to the program for a timing signal, and a semiconductor device testing apparatus using such timing signal generating apparatus.
2. Description of the Related Art
A timing signal generating apparatus for generating a timing signal on the basis of a program is used in, for example, a semiconductor device testing apparatus for testing a semiconductor device.
FIG. 11
shows an example of a conventional semiconductor device testing apparatus (hereinafter referred to as an IC tester) for testing a semiconductor integrated circuit element (hereinafter referred to as an IC) which is a typical example of a semiconductor device. This IC tester TES comprises, roughly speaking, a main controller
111
, a pattern generator
112
, a timing generator
113
, a waveform formatter
114
, a logical comparator
115
, a driver group
116
, an analog level comparator group
117
, a failure analysis memory
118
, a logical amplitude reference voltage source
121
, a comparison reference voltage source
122
, and a device power supply
123
.
The main controller
111
is generally comprised of a computer system and mainly controls the pattern generator
112
and the timing generator
113
in accordance with a test program PM created by a user.
First of all, prior to starting an IC test, a set of various data is performed by the main controller
111
. After those various data are set, the IC test is started. By supplying a test start command from the main controller
111
to the pattern generator
112
, the pattern generator
112
starts to generate a pattern. Therefore, a time point when the pattern generator
112
starts to generate a pattern is a time point when the test is started. The pattern generator
112
supplies a test pattern data to the waveform formatter
114
in accordance with the test program. On the other hand, the timing generator
113
generates a timing signal (clock pulses) for controlling the operation timings of the waveform formatter
114
, the logical comparator
115
and the like.
The waveform formatter
114
converts a test pattern data supplied from the pattern generator
112
to a test pattern signal having a real waveform. This test pattern signal is applied to an IC under test (generally referred to as a DUT)
119
via the driver group
116
for amplifying voltage of the test pattern signal to a waveform having an amplitude value set in the logical amplitude reference voltage source
121
, and is stored in a memory of the IC under test
119
.
On the other hand, a response signal read out from the IC under test
119
is compared by the a logical comparator
117
with the a reference voltage supplied from the comparison reference voltage source
122
to determine whether or not the response signal has a voltage of a predetermined logical level (a voltage of logical H (logical high) or a voltage of logical L (logical low)). The response signal determined to have the predetermined logical level is sent to the logical comparator
115
, where the response signal is compared with an expected value pattern signal outputted from the pattern generator
112
.
If the response signal is not equal to the expected value pattern signal, a memory cell having an address of the IC under test
119
from which the response signal was read out is determined to be in failure, and a failure signal indicating this is generated. Usually this failure signal is expressed by a logical “1” signal, and is stored in the failure analysis memory
118
. A failure signal is generally stored in an address of the failure analysis memory
118
that is same as that of the IC under test
119
.
On the contrary, if the response signal is equal to the expected value pattern signal, a memory cell having an address of the IC under test
119
from which the response signal was read out is determined to be normal, and a pass signal indicating this is generated. This pass signal is expressed by a logical “0” signal, and is not usually stored in the failure analysis memory
118
.
When the test is completed, the failure signals stored in the failure analysis memory
118
are read out therefrom, then, for example, whether or not a relief of the failure memory cells of the tested IC
119
is possible is determined.
The timing generator
113
generates a timing signal (clock pulses) for defining a rising timing and a falling timing of the waveform of the test pattern signal to be applied to the IC under test
119
, a timing signal (clock pulse) of a strobe pulse for defining a timing of a logical comparison between the response signal and the expected value pattern signal in the logical comparator
115
, and the like.
The IC tester is constructed such that the timings and/or periods for generating those timing signals are described in a test program PM created by the user, and the test pattern signal is applied to the IC under test
119
at operation periods and timings intended by the user to operate the IC under test, and in addition, a test can be performed to see if the operation is normal.
Next, an outline of the timing generator
113
and the waveform formatter
114
will be described with reference to FIG.
12
.
FIG. 12
shows a schematic configuration of the waveform formatter and the timing generator for generating one channel test pattern signal. As illustrated, the waveform formatter
114
can be constituted by an S-R (set/reset) flip-flop FF, which can generate a test pattern signal TP rising at a predetermined timing T
1
and falling at a predetermined timing T
2
by supplying a set pulse P
S
to its set terminal S and by supplying a reset pulse P
R
to its reset terminal R.
Those set pulse P
S
and reset pulse P
R
are generated by a pair of clock generators
113
A and
113
B, respectively. Delay data DY
S
and DY
R
read out from a delay data memory
113
C are supplied to those clock generators
113
A and
113
B, respectively, and a generation timings of the set pulse P
S
and the reset pulse P
R
are defined by the delay data DY
S
and DY
R
, respectively.
The delay data memory
113
C is accessed by an address signal supplied from an address counter
113
D. The address counter
113
D generates, from the test starting time, an address signal the address of which is incremented by +1 in every test period TS
RAT
(refer to FIG.
13
). Therefore, the delay data memory
113
C is accessed, in every test period TS
RAT
during the test, by the address signal the address of which is incremented by +1 in the sequential order, and the delay data DY
S
and DY
R
set therein in advance are read out therefrom in every test period TS
RAT
. Those delay data DY
S
and DY
R
are set in the clock generators
113
A and
113
B, respectively, and the set pulse P
S
and the reset pulse P
R
are generated based on those delay data, respectively.
The above operation will be described with reference to FIG.
13
. The clock generator
113
A generates a set pulse P
S
shown in
FIG. 13B
at a timing delayed by the set delay data DY
S1
from, for example, a rising timing of a rate clock RAT shown in
FIG. 13A
defining a test period TS
RAT
during the test. In addition, the clock generator
113
A generates a reset pulse P
R
shown in
FIG. 13C
at a timing delayed by the set delay data DY
R1
from a rising timing of the rate clock RAT. By the above operation, a test pattern signal TP shown in
FIG. 13D
having a pulse duration corresponding to a time difference T
PW
from a generation timing of the set pulse P
S
to a generati
Advantest Corporation
Gallagher & Lathrop
Lathrop David N.
Miska Vit
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