Timing-signal delay equipment

Details Timing-signal delay equipment Timing-signal delay equipment

1988-01-15

1990-07-03

Lall, Parshotam S.

Boots, shoes, and leggings

307514, 371 27, 324158R, G04F 500, H03K 513

Patent

active

049396773

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The Invention relates to timing-signal delay equipment that gives a predetermined set-up value of delay time to a timing signal.


BACKGROUND OF THE INVENTION

FIG. 7 shows one of the conventional timing-signal delay equipment where an input timing signal Q1 is supplied to a logic gate 1 whose output is connected to a cascade circuit G composed of n delay elements D.sub.1 -D.sub.n connected serially, each of which is of the same structure comprising a resistor R and a variable capacitor C as shown. The binary coded error information E, which is defined to represent the difference between a predetermined set-up value of delay time and the delay time of an output timing signal Q2 actually obtained at the cascade circuit G to its input timing signal Q1, makes a D/A converter B generate an analog control signal that controls the capacitance of each variable capacitor in delay elements D.sub.1 -D.sub.n so that the delay time of output timing signal Q2 to its input timing signal Q1 becomes almost equal to said set-up value.
FIG. 8 shows another conventional timing-signal delay equipment which has a cascade circuit G composed of a waveform converter 11 which converts an input timing signal Q1 to a triangular waveform, whose output is connected to a threshold gate circuit 12. A D/A converter B with error information E of the same definition as before at its input, provides an analog control signal that controls the threshold level of the threshold gate circuit 12 so that the delay time of an output timing signal Q2 obtained at the cascade circuit G to its input timing signal Q1 becomes almost equal to said set-up value.


DISADVANTAGES TO BE SOLVED BY THE INVENTION

The type of timing-signal delay equipment shown in FIG. 7, however, has the following drawback. As the degree of precision in the delay time given by the equipment a timing signal depends on the fineness in structure of the D/A converter B, which makes it difficult to integrate the whole circuitry into a small size and with high density with IC technology.
The same is true for the type of timing-signal delay equipment shown in FIG. 8, where the waveform converter 11, threshold gate circuit 12, and the D/A converter B should be of finely controlled structure in order to generate an output timing signal with a precisely specified delay time.


SUMMARY OF THE INVENTION

The object of the invention, accordingly, is to provide new types of timing-signal delay equipment without above drawback.
A type of timing-signal delay equipment noted in the first invention of this specification has a cascade circuit composed of a plural number (=n) of delay circuits U.sub.1 -U.sub.n connected serially, each of which has a plural number (=m) of delay elements D.sub.1 -D.sub.m that give mutually different m values of delay time to a timing signal, and has a selection circuit connected to its input side or output side for selecting one of said m delay elements D.sub.1 -D.sub.m on receiving control information, and said timing-signal delay equipment has also an arithmetic control circuit which receives both set-up information representing a predetermined set-up value of delay time that an output timing signal should have to its input timing signal and error information representing the difference between the delay time of an output timing signal obtained at the cascade circuit to its input timing signal and said set-up value and performs necessary calculations with them to generate said control information to each selection circuit of said delay circuits U.sub.1 -U.sub.n so that said output timing signal obtained at said cascade circuit has a delay time to said input timing signal whose value is an optimum approximation to said set-up value.
A type of timing-signal delay equipment noted in the second invention has a cascade circuit that comprises two circuit units connected serially. The first circuit unit is composed of a plural number (=n) of main delay circuits U.sub.1 -U.sub.n connected serially, each of which has a plural number (=m) of delay el

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"Variable Delay Circuits with 50 ps Timing Resolution", by Hayashi, K. Muraju, and N. Aoki, Abstract of Presentation in National Convention Record in 1984 of the Institute of Electronics and Communication Engineers in Japan (IECE), Communication Section, No. 100, p. 1-100 (one page), Oct. 1984.

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