Timing signal delay circuit with high resolution or accuracy

Details Timing signal delay circuit with high resolution or accuracy Timing signal delay circuit with high resolution or accuracy

1990-12-10

1992-03-10

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307595, 307597, 307602, 307603, 307605, 328 55, 3281291, 377 20, H03K 5159, G01R 2902, G01D 0000

Patent

active

050952323

ABSTRACT:
A timing signal delay circuit comprises a counter placed with first delay setting data (21-24) for counting a first clock signal (12) in response to an input timing pulse (11), and a first flip-flop circuit which has a D-input supplied with the output of the counter (1) and a clock input supplied with a second clock signal of the same timing frequency as the first clock signal. For doubling resolution of the delay which the input timing pulse undergoes, there are provided an exclusive-OR gate (4) supplied with a second dealy data signal (31) and a third clock signal (14) of the same timing as the second clock signal (13), an AND gate (5) supplied with the output of the exclusive-OR gate (4) and that of the first flip-flop (3), and a second flip-flop supplied with the output of the AND gate (5) and a fourth clock signal (15) having twice as high frequency as that of the first clock (12). The input timing pulse can be delayed with high resolution or accuracy.

REFERENCES:
patent: 3725793 (1973-04-01), Phillips
patent: 4626716 (1986-12-01), Miki
patent: 4800304 (1989-01-01), Takeuchi
patent: 4845390 (1989-07-01), Chan

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