Timing scheme for memory arrays

Details Timing scheme for memory arrays Timing scheme for memory arrays

1997-10-24

1999-07-13

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36523001, 36523006, 3652335, G11C 700

Patent

active

059236108

ABSTRACT:
A DRAM includes a data input buffer having a first input terminal coupled to data I/O pins, a second input terminal coupled to a column address buffer, a third input terminal coupled to a column address strobe buffer, and an output terminal coupled to a column decoder. When reading a selected cell of the DRAM, the first row address and the first column address are latched on the falling edge of the row address strobe signal from the address input pins into a row address buffer and from the I/O pins into the data input buffer, respectively, of the DRAM. While the row address is decoded and used to select a row of memory cells of the DRAM, the column address is decoded and used to select one of the cells from the selected row. Data corresponding to the selected cell is forwarded to the I/O pins on the first falling edge of the column address strobe signal. By latching both the first row address and the first column address on the falling edge of the row address strobe signal, the access time of the first column address is hidden.

REFERENCES:
patent: 5226139 (1993-07-01), Fujishima et al.
patent: 5274596 (1993-12-01), Watanabe
patent: 5335206 (1994-08-01), Kawamoto
patent: 5521878 (1996-05-01), Ohtani et al.
patent: 5588130 (1996-12-01), Fujishima et al.
patent: 5764576 (1998-06-01), Hidaka et al.

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