Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
1999-11-09
2002-03-26
Corrielus, Jean (Department: 2631)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C375S371000, C331S002000, C331S046000
Reexamination Certificate
active
06363129
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to clock signals in a transceiver. More particularly, the present invention relates to a method and an apparatus for generating and distributing clock signals in a gigabit Ethernet transceiver which includes more than one constituent transceiver.
2. Description of Related Art
A transceiver includes a transmitter and a receiver. In a traditional half-duplex transceiver, the transmitter and the receiver can operate with a common clock signal since the transmitting and receiving operations do not occur simultaneously.
In a full-duplex transceiver, the transmitting operation occurs simultaneously with the receiving operation. The full-duplex transceiver needs to operate with at least two clock signals, a transmit clock signal (TCLK) and a sampling clock signal. The TCLK signal is used by the transmitter to regulate transmission of data symbols. The sampling clock signal is used by the receiver to regulate sampling of the received signal at an analog-to digital (A/D) converter. At the local receiver, the frequency and phase of the sampling clock signal are adjusted by a timing recovery system of the local receiver in such a way that they track the transmit clock signal of the remote transmitter. The sampled received signal is demodulated by digital signal processing function blocks of the receiver. These digital processing functions blocks may operate in accordance with either the TCLK signal or the sampling clock signal, provided that signals crossing boundaries between the two clock signals are treated appropriately so that any loss of signal or data samples is prevented.
The IEEE 802.3ab standard (also called 1000BASE-T) for 1 gigabit per second (Gb/s) Ethernet full-duplex communication system specifies that there are four constituent transceivers in a gigabit transceiver and that the full-duplex communication is over four twisted pairs of Category-5 copper cables. Since a Gigabit Ethernet transceiver has four constituent transmitters and four constituent receivers, its operation is much more complex than the operation of a traditional full-duplex transceiver. The four twisted pairs of cable may introduce different delays on the signals, causing the signals to have different phases. This, in turn, requires the gigabit Ethernet transceiver to have four A/D converters operating in accordance with four respective sampling clock signals. In addition, the problem of switching noise coupled from the digital signal processing blocks of the gigabit Ethernet transceiver to the four A/D converters must also be addressed.
Therefore, there is a need to have an efficient method and system for generating the clock signals for a gigabit Ethernet transceiver. There is also a need to distribute the clock signals such that effect of switching noise is minimized.
SUMMARY OF THE INVENTION
The present invention provides a method and a timing recovery system for generating a set of clock signals in a system which includes a set of subsystems. Each of the subsystems includes an analog section. The set of clock signals includes a set of sampling clock signals. Each of the analog sections operates in accordance with a corresponding one of the sampling clock signals. For each of the sampling clock signals, a phase error is generated from a corresponding phase detector. The phase errors are filtered by a set of corresponding loop filters. The filtered phase errors are provided to a set of corresponding oscillators to generate phase control signals. The phase control signals are provided to a set of corresponding phase selectors to generate the sampling clock signals.
REFERENCES:
patent: 4659999 (1987-04-01), Motoyama et al.
patent: 5128633 (1992-07-01), Martin et al.
patent: 5142377 (1992-08-01), Moriyama et al.
patent: 5428361 (1995-06-01), Higtower et al.
patent: 5548249 (1996-08-01), Sumita et al.
patent: 5572167 (1996-11-01), Alder et al.
patent: 5644271 (1997-07-01), Molloy et al.
patent: 5726607 (1998-03-01), Brede et al.
patent: 5978390 (1999-11-01), Balatoni
patent: 6041090 (2000-03-01), Chen
patent: WO 98/09400 (1998-05-01), None
patent: WO 99/07077 (1999-02-01), None
IEEE Std 802.3ab-1999 (Supplement to IEEE Std 802.3, 1998 Edition), entitled Supplement to Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications—Physical Layer Parameters and Specifications for 1000 Mb/s Operation Over 4-Pair of Category 5 Balanced Copper Cabling, Type 1000BASE-T.
Search Report dated Sep. 5, 2000 relating to corresponding International Application No. PCT/US00/11123, 4 pp.
Local and Metropolitan Area Networks, Specific Requirements, Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications; IEEE Std 802.3, 1998 Edition; pp. 893-963: LAN MAN Standards Committee of the IEE Computer Society; USA.
Agazzi et al.; Two-Phase Decimation and Jitter Compensation in Full-Duplex Data Transceivers; Proceedings of the International Symposium on Circuits and Systems; Mar. 10, 1992; pp. 1717-1720; IEEE; USA.
Hatamian et al.; Design Considerations for Gigabit Ethernet 1000Base-T Twisted Pair Transceivers; 1998; pp. 335-342; IEEE 1988 Custom Integrated Circuits Conference.
Broadcom Corporation
Christie Parker & Hale LLP
Corrielus Jean
LandOfFree
Timing recovery system for a multi-pair gigabit transceiver does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Timing recovery system for a multi-pair gigabit transceiver, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing recovery system for a multi-pair gigabit transceiver will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2877566