Timing recovery system

Details Timing recovery system Timing recovery system

1999-02-03

2001-08-14

Le, Amanda T. (Department: 2634)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S355000, C375S376000, C348S537000

Reexamination Certificate

active

06275548

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to electronic circuits, and more particularly, to timing recovery circuits and methods.
In high speed modems for digital communication the timing recovery by the receiver synchronizes the symbol rate of the receiver to that of the transmitter.
FIG. 1
shows an overall system with transmitter, receiver, converters and channel. The data rate over the channel for cable modems could be 20 MHz. The digital-to-analog and analog-to-digital converters could also run at the data rate. Because the transmitter and receiver are physically isolated from each other by the channel, their clocks could run at slightly different rates. A worst case rate difference could be on the order of 50 ppm. The channel could also introduce some phase errors into the signals and this needs to be corrected. The job of the timing recovery portion of the receiver is to correct both the phase errors and the frequency errors of the transmitter and receiver systems.
To correct for frequency errors, the digital timing recovery must be able to control the clocking of the receiver clock. If the transmitter clock is operating at the exact frequency of the receiver clock, then there is no error. But this is rarely the case. Usually, the two clocks will oscillate at slightly different frequencies. If the transmitter clock is slower than the receiver clock, then the receiver must be able to subtract a sample. And if the transmitter clock is faster than the receiver clock, then the receiver must be able to add a sample. The receiver typically samples the signal at a rate higher than the symbol rate. The timing recovery may perform these functions with an interpolator filter and some logic which generates a valid_out signal. The valid_out signal is nominally running at the sample rate which for cable modems is 20 MHz. If the timing recovery determines that it needs to add a sample or subtract a sample, then the output of the valid_out will look as illustrated in FIG.
2
.
The timing recovery corrects phase errors by first determining the phase error of the channel. Next, it calculates the opposite of this phase which is used in the interpolator filter to cancel out the channel phase error. The output of the interpolator filter is the corrected samples to be used in the demodulator. The precision of the phase is related to the granularity of the interpolator coefficients. For a cable modem, typically the unit circle is divided into 128 slices with each slice corresponding to a (quantized) phase. The job of the timing recovery is to determine the phase error and pick one of the possible 128 sets of coefficients so that the interpolator filter can correct it.
One of the most popular timing recovery schemes in digital quadrature amplitude modulation (QAM) systems such as cable modems uses band edge component maximization (BECM). Godard originally proposed the BECM in 1978; see Godard, Passband Timing Recovery in an All-Digital Modem Receiver, 26 IEEE Tr. Comm. (May 1978). The BECM circuit produces timing phase estimates at the symbol rate, which are then passed to a loop filter.
U.S. Pat. No. 5,802,461 shows a variant of BECM applied to vestigial sideband modulation. The variant BECM output is filtered and the phase extracted to control a voltage controlled oscillator (VCO) which drives the analog-to-digital converter (ADC) sampling as illustrated in FIG.
3
.
SUMMARY OF THE INVENTION
The present invention modifies the band edge component maximum (BECM) to generate timing phase estimates at the sample rate rather than the symbol rate, and a phase locked loop (PLL) averages the estimates and feeds back control at a low rate.
This has the advantage of increasing the speed of convergence and stability of the timing recovery loop.


REFERENCES:
patent: 5872815 (1999-02-01), Strolle et al.
patent: 6148037 (2000-11-01), Abe

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