Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
1998-05-12
2001-08-21
Chin, Stephen (Department: 2634)
Pulse or digital communications
Receivers
Angle modulation
C375S327000, C375S344000, C329S306000, C329S307000, C331S018000
Reexamination Certificate
active
06278746
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of timing recovery in modems and in particular to a timing recovery loop circuit in a receiver of a modem.
BACKGROUND OF THE INVENTION
In communication systems a modem is used to convert (modulate) digital signals generated by a computer into analog signals suitable for transmission over telephone lines. Another modem, located at the receiving end of the transmission, converts (demodulates) the analog signals back into digital form. Timing recovery refers to, and includes, the generation and/or reconstruction of a clock signal, at a receiver, to sample the incoming signal. The clock signal generated at the receiver end must agree in frequency with the transmitter clock at the sending end and may also require proper phasing.
To recover data from a Quadrature Amplitude Modulated (QAM) signal (for example), a receiver is required to convert the analog signal received into a digital signal and to distinguish between the individual symbols that comprise the signal bitstream. Symbol timing recovery is used to recover a clock signal at the symbol rate, or a multiple of the symbol rate, from the modulated waveform that is received. This clock signal may be used by the receiver to convert the continuous-time received signal into a discrete-time sequence of data symbols.
Traditional recovery circuits are typically functionally limited to a small operating range. When the signal loss and distortion vary over a large dynamic range, the behaviour of the circuit changes dramatically due to the large variability in the circuit's s-curve maximum amplitude for different channels.
An s-curve is a curve showing the output of a phase detector in a timing recovery circuit as the phase difference between a received signal phase and an ideal phase between 0 and 2&pgr;. The amplitude of the s-curve can be viewed as a measure of the quality of the timing recovery. In particular, robust and accurate timing recovery in a modem receiver generates a large maximum amplitude of the s-curve. If the s-curve maximum amplitude is reduced (due to loss, distortion, etc.), it results in long acquisition times and large phase jitter after acquisition. This problem is accentuated by the use of various QAM constellations, slope equalizer settings, and by the presence of radio frequency interference (RFI) from commercial AM broadcasts.
In general, traditional timing recovery, in modem receivers is based on standard phase-locked loop (PLL) circuitry (i.e. phase detector, loop filter, and oscillator). Some systems use the output of a timing tone circuit as an input signal. The timing tone circuit derives a tone from the incoming signal having a frequency that is equal to the symbol rate. Further, typical phase detectors are based on decisions about the received signal.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a timing recovery loop circuit that operates for a relatively large range of bandwidths and QAM orders.
Another object of the present invention is to provide a timing recovery loop circuit that provides flexibility in establishing fast acquisition times and reduced phase jitter after acquisition.
In accordance with an aspect of the present invention there is provided a receiver circuit having means for receiving and sampling an analog input signal to generate a digital signal controlled by a voltage controlled oscillator supplying a timing signal; said receiver circuit comprising: a digital matched filter for filtering the digital signal to generate an in-phase signal and a quadrature-phase signal; a phase detector for generating an instantaneous phase error signal based on the in-phase and a quadrature-phase signals; and filtering means for averaging the instantaneous phase error signal over time to generate an average phase error signal for adjusting the timing signal supplied by the oscillator to the means for receiving and sampling the analog input signal.
In accordance with another aspect of the present invention there is provided a symbol timing recovery circuit, comprising: a voltage controlled oscillator for generating a timing signal as a function of an average phase error signal; an analog-to-digital converter for generating a digital signal from an input analog signal based on the timing signal; a digital matched filter for filtering the digital signal to generate an in-phase signal and a quadrature-phase signal; a phase detector circuit for generating an instantaneous phase error signal of the in-phase and quadrature-phase signals; a digital loop filter for receiving the instantaneous phase error signal over time to generate the average phase error signal; a digital-to-analog converter for converting the average phase error signal into analog; and an analog loop filter for receiving and conditioning the average phase error signal from the digital loop filter converted by the digital-to-analog converter, wherein the average phase error signal adjusts the timing signal generated by the oscillator.
In accordance with another aspect of the present invention there is provided a symbol timing recovery circuit, comprising: a voltage controlled oscillator for generating a sampling clock as a function of an average phase error signal; the oscillator having a nominal frequency and an output for outputting the sampling clock; an analog-to-digital converter for generating a digital signal from an input analog signal; said analog-to-digital converter having an output for outputting the digital signal, an analog signal input for receiving the input analog signal, and a sampling frequency control signal input coupled to the output of the oscillator for receiving the timing signal and for controlling the rate at which the analog-to-digital converter samples the analog signal; a digital matched filter for filtering the digital signal to generate an in-phase signal and a quadrature-phase signal; the digital matched filter includes an input coupled to the digital signal output of the analog-to-digital converter for receiving the digital signal, and a first output for outputting the in-phase signal and a second output for outputting the quadrature-phase signal; a phase detector circuit for generating an instantaneous phase error signal of the in-phase and quadrature-phase signals; a digital loop filter for receiving the instantaneous phase error signal over time to generate the average phase error signal; a digital-to-analog converter for converting the average phase error signal into analog; and an analog loop filter for receiving and conditioning the average phase error signal from the digital loop filter converted by the digital-to-analog converter, wherein the average phase error signal adjusts the nominal frequency of the oscillator to output the sampling clock.
In accordance with another aspect of the present invention there is provided a method of generating a symbol timing signal from an analog signal, the method comprising the steps of: operating a voltage controlled oscillator in response to an average phase error signal to generate a timing signal having a sampling frequency fs; operating an analog-to-digital converter to receive the analog signal, to receive the timing signal, and to generate a digital signal by sampling the analog signal at the frequency fs; filtering the digital signal to generate an in-phase signal and a-quadrature-phase signal; sampling the in-phase signal to generate an in-phase error signal; sampling the quadrature-phase signal to generate a quadrature-phase error signal; summing the in-phase error signal and the quadrature-phase error signal to obtain an instantaneous phase error signal; and filtering the instantaneous phase error signal over a prescribed period of time to obtain the average phase error signal.
In accordance with another aspect of the present invention there is provided a method of obtaining and maintaining timing lock in a modem receiver comprising: initializing a digital loop filter having a gain parameter and a frequency pole parameter, where the gain parameter is assigne
Dublin Ian
Velez Edgar
Chin Stephen
Deppe Betsy L.
Montreal Networks Limited
Swabey Ogilvy Renault
Wood Max R.
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