Television – Synchronization – Automatic phase or frequency control
Reexamination Certificate
1999-12-21
2003-06-24
Miller, John (Department: 2714)
Television
Synchronization
Automatic phase or frequency control
C348S725000, C348S516000, C348S521000, C348S536000, C375S355000
Reexamination Certificate
active
06583822
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital television receiver and more particularly to a timing recovery device in a digital television receiver using a vestigial side band (VSB) system.
2. Discussion of Related Art
As the next generation of digital TV system, the High Definition Television (HDTV) has been continually developing to ultimately bring the theater right into the living room of a viewer. When compared with an existing analog TV, a digital TV not only has a higher resolution and a larger size in the horizontal direction, but produces a vivid sound comparable to a compact disc via a multi-channel. However, due to the many ways to transmit the data, a standardization of the digital TV (DTV) is still being settled among companies mainly in U.S.A, Europe and Japan.
In U.S.A., a VSB system proposed by Zenith has been adapted as a transmission format, a Motion Picture Expert Group (MPEG) has been adapted as a video compression format, a Dolby AC-3 has been adapted as an audio compression format, and an existing but compatible display method has been adapted as a display format. To transmit compressed image data under the above standards for a DTV, an error correction coding (ECC) is executed on the compressed image data. Particularly, a synchronizing signal is inserted between data at predetermined periods before transmission, thereby facilitating the recovery of the data at a receiving side.
The synchronizing signal is classified into two kinds, where one is a horizontal synchronizing (hsync) signal commonly called ‘a data segment synchronizing signal’, and the other is a vertical synchronizing (vsync) signal commonly called ‘a field synchronizing signal’. The hsync and vsync signals of the digital TV differ from the horizontal and vertical synchronizing signals of a National Television System Committee (NTSC) television.
FIG. 1
shows a transmission signal frame of the digital TV in a VSB system. As shown, one frame is comprised of two fields, where each field includes 313 data segments and where each data segment includes 832 symbols of 4 hsync signals and 828 data symbols. Because the hsync signal does not undergo the ECC process, each data segment includes 4 symbols of hsync signal and 828 symbols of ECC signal. Also, one of the 313 data segments in each field is a vsync segment containing a training sequence and the remaining 312 are general data segments.
Also, before transmission from a transmitting side such as a broadcasting station, the signal to be transmitted is passed through a mapper by which the signal is changed into desired power levels. For a terrestrial broadcasting type of 8 VSB, the output level of the mapper corresponds to one of 8-step symbol values (amplitude level) −7, −5, −3, −1, 1, 3, 5, 7. Moreover, according to a predetermined agreement, the mapper forcibly inserts the 4 symbols of the hsync signal for every 832 symbols and forcibly inserts the vsync signal in the position of every 313th data segments.
Furthermore, with two logic levels, a prescribed logic level of the hsync signal ‘1, 0, 0, 1’ is continually repeated in every data segment. The output level of the mapper is ‘5’ if the hsync signal is in a logic level of ‘1’ and the output level of the mapper is ‘−5’ if the hsync signal is in a logic level of ‘0’. Namely, the hsync signal has only the two logic levels, which are continually repeated in every data segment.
FIG. 2
shows a receiving side such as a digital TV receiver in the related art. The receiving side receives a Radio Frequency (RF) signal modulated by a VSB mode through an antenna. A tuner
21
tunes the RF signal to select a frequency of a desired channel and converts the selected frequency into an Intermediate Frequency (IF). A Frequency Phase Locked Loop unit (FPLL)
22
demodulates the IF signal into base band signals I and Q, and locks both the frequencies and the phases. Specifically, the FPLL
22
is a circuit integrating a frequency tracking loop FLL and a phase locked loop (PLL). Thus, the FPLL unit
22
first locks a frequency and upon locking the frequency, locks a phase.
The Q signal is used for the recovery of a carrier in the FPLL
22
while an analog-to-digital (A/D) converter
23
converts the I signal from the FPLL
22
into a digital signal of fixed bits (for example 10 bits). Using the digital signal of fixed bits, the sync signal recovery unit
24
recovers the hsync signal and the field synchronizing signal inserted by the transmission side. The synchronizing signals are used in a timing recovery and an equalization.
Particularly, the synchronizing signals are output to an equalizer/ECC
26
. The hsync signal and the field synchronizing signal may be interfered by linear distortion of amplitude and ghost resulting from signal reflections off of structures such as buildings and mountains. Accordingly, the equalizer/ECC
26
conducts an equalization utilizing the restored hsync signal and the field synchronizing signals as training signals to correct interferences to the data, and conducts ECC to correct any errors caused during the transmission through the transmission channel. A video decoder
27
then decodes the equalized and error corrected signal utilizing a Moving Picture Expert Group (MPEG) algorithm and the decoded signals are displayed to the viewers.
Moreover, data is transmitted according to an Advanced Television Systems Committee (ATSC) VSB transmission system proposed in a U.S. digital TV. At the receiving side, as shown in
FIG. 2
, a same clock as was used in the transmitting side should be generated to recover the transmitted data. This timing recovery is generated by implementing a timing recovery unit
25
. Under the current proposed ATSC standard, the timing recovery is implemented by using the hsync signals inserted by the transmitting side.
FIG. 3
is a block diagram of a timing recovery device of a digital TV in the related art. As shown, the timing recovery unit
25
includes a timing error detector
31
which extracts the timing error information from the digital signal output by the A/D converter
23
; a loop filter
32
which filters only a low frequency signal component of the timing error information; and a voltage controlled oscillator (VCO)
35
which converts an output frequency in accordance with the low frequency signal component of the timing error information to adjust the sampling timing of the A/D converter
23
. In this case, the timing error detector
31
receives a control signal from the synchronizing recovery unit
24
to determine a section of the digital signal for performing a timing recovery. Particularly,
FIG. 4
shows a block diagram of a hsync signal recovery unit
24
as disclosed in a co-pending application Ser. No. 09/131,387 entitled “Signal Recovery System,” which is fully incorporated herein.
As shown in
FIG. 4
, the signal recovery unit
24
includes a correlating detector
41
which determines a correlation relation of the digital signal output by the A/D converter
23
with a known hsync signal pattern, i.e. searches for successive groups of the four symbols of the hsync signal within the digital signal; an integrator
42
which adds the data output by the correlating detector
41
for a period of 832 symbols to distinguish the hsync signal section from the data section; a slicer
43
which compares the output value of the integrator
42
with a first predetermined threshold value and outputs a signal indicating the hsync signal section if the output value is over the first predetermined threshold value; and a confidence counter
44
which checks the reliability of the hsync signal section output by the slicer
43
and outputs the control signal indicating a recovery of the hsync signal and the recovered hsync signal if the checked reliability is above a second predetermined value.
Accordingly, the timing error detector
31
of the timing recovery unit
25
extracts the timing error information from the digital signal output by the A/D converter
31
and deter
Birch & Stewart Kolasch & Birch, LLP
Desir Jean W.
LG Electronics Inc.
Miller John
LandOfFree
Timing recovery device of digital TV does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Timing recovery device of digital TV, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing recovery device of digital TV will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3156990