Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Patent
1995-06-07
1997-04-29
Bocure, Tesfaldet
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
375365, 375329, H04L 700, H04L 2722
Patent
active
056256523
ABSTRACT:
A digital demodulator and method for demodulating digital data representing a phase shift keyed (PSK) signal are provided. The demodulator comprises a phase detector, automatic frequency controller, automatic timing recovery controller, data decoder, and unique word detector. According to the method of the present invention, a PSK signal is received and digitized to substantially remove the signal's amplitude characteristics. The phase detector receives an input of the digital data and based upon transitions in the data from a high state to low state and from a low state to a high state, provides phase estimates. The phase estimates are converted by the data decoder into binary data representing the symbols transmitted to form the PSK signal. A number of overlapping windows of digital data are used to determine phase estimates. The unique word detector receives an input of binary data from the data decoder and using a correlation technique identifies one set of windows which substantially maximizes synchronization of the demodulator with the received PSK signal. After the synchronizing window has been identified the automatic frequency controller monitors any frequency drift of the PSK signal and corrects the phase estimates based on the frequency error. The automatic timing recovery controller uses the corrected phase errors from early and late windows with respect to the synchronizing window to adjust the timing of the synchronizing window by advancing or delaying the demodulator's symbol timing signal to further maximize synchronization with the received PSK signal.
REFERENCES:
patent: 4232197 (1980-11-01), Acambora et al.
patent: 4514697 (1985-04-01), York
patent: 5235622 (1993-08-01), Yoshida
patent: 5241567 (1993-08-01), Shimakata
patent: 5259005 (1993-11-01), LaRosa et al.
patent: 5345440 (1994-09-01), Gledhill et al.
David C. Chu, Article Entitled "Phase Digitizing; A New Method for Capturing and Analyzing Spread-Spectrum Signals", Hewlett-Packard Journal Feb. 1989, pp. 28-35.
Kerry Hanson, "Single Chip Unlocks Phase-Shift Keying for 1200-bit/s Modem", Electronic Design Jun. 14, 1984, pp. 261-268.
Al Mouton, "transceiver ICS Adapt to Use With All Types of Voice-Data Networks", Electronic Design Jul. 11, 1985, pp. 137-142.
Article entitled "Digital Quadrature PSK Builds One-Chip Modem to Meet 212A Standards", Electronic Design Feb. 21, 1985, pp. 47 & 48.
Article entitled "True One-Chip Modem Blazes Design Trail", Electornics, Nov. 4, 1985, pp. 46-48.
David Taylor, Steve Edison & Sidhartha Maitra, Article Entitled "1200-bit/s Modem Chip Puts Board-Level Power Onto Any Processor Bus", Electronic Design Jan. 23, 1986, pp.
Richard L. Hall, Article Entitled "Design of Fast Modems Gets Simpler With DPSK Chip Set", Electronic Design Jan. 12, 1984, pp. 325-330.
Dave Bursky, Article Entitled "Single-Chip Modem Goes Worldwide at 2400 bits/s", Electronic Design Aug. 7, 1986, pp. 53 & 54.
Article Entitled "Mainframe Server Links Ethernets to IBM's SNA", Electronics Jul. 24, 1986, pp. 148 & 149.
L. Brett Glass, Article Entitled "Modern Modem Methods", BYTE Jun. 1989, pp. 321-326.
Bocure Tesfaldet
Jaquez Martin J.
Pacific Communication Sciences, Inc.
Richman, III Merle W.
LandOfFree
Timing recovery controller and method for adjusting the timing o does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Timing recovery controller and method for adjusting the timing o, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing recovery controller and method for adjusting the timing o will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-712205