Timing recovery circuit with multiple stages

Details Timing recovery circuit with multiple stages Timing recovery circuit with multiple stages

2007-02-06

2007-02-06

Nguyen, Linh (Department: 2819)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S376000, C375S375000, C375S354000

Reexamination Certificate

active

11357031

ABSTRACT:
A timing recovery circuit includes a first oscillating circuit configured to produce a first timing signal, a second oscillating circuit configured to produce a second timing signal, a first decimation circuit coupled to a supply node of a first clock signal and to the first oscillating circuit to produce a second clock signal made by decimating pulses of the first clock signal in response to the first timing signal, and a second decimation circuit coupled to the first decimation circuit and to the second oscillating circuit to produce a third clock signal made by decimating pulses of the second clock signal in response to the second timing signal, wherein one of the first timing signal and the second timing signal has a fixed cycle, and another one has a cycle responsive to feedback control.

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